Jaswinder Ahuja: IoT and its consequences of the semiconductor chip design
A new year has dawned and with it emerge fresh new challenges for design engineering teams and for us as key ecosystem partners. The challenges we’ll face in the next 12 months will no doubt be as tough as what we conquered as an industry in 2014, but that’s why we love this industry.
Let’s take a look at some areas of both challenge and opportunity in 2015.
Despite forecasts of the early demise of Moore’s Law, advanced node development continues apace. Indeed, I’ve been surprised in 2014 that, given the fact that 16nm and 14nm nodes have not yet ramped to volume, several companies already are looking at 10nm readiness. And they have plans to do test chips as early as mid-2015. Waiting just off stage, of course, is 7nm. These transitions are going to test all of us as innovators.
But we’ve already begun to put in place an industry structure to tackle these tough challenges. “Vertical co-optimization” has been an important innovation in advanced node enablement. Essentially, it turns a process that was a series of steps into a parallel process. While the serial process was easy to manage because each step was self-contained, it yielded sub-optimal results and could be time-consuming.
In contrast, the vertical co-optimization approach offers a multitude of opportunities to see how decisions in one realm affect the other elements of the system design enablement ecosystem. This change allows mutual trade-offs for optimization versus the old model of optimizing one step, holding it fixed, and passing the outcome onto the next step.
From a Cadence standpoint, our priority always is to have the design infrastructure ready in time. We already understand the unique challenges that 10nm represents beyond what we’ve done at 16/14nm and the deep ecosystem partnership necessary to enable those systems.
IoT and its Consequences
On the applications side of the ledger, the IoT is, if you think about it, the mother of all trends. It encompasses everything: mobility, wearables, cloud, big-data, analytics, devices, semiconductors and more. I think that, in itself, further amplifies some of the challenges the industry has seen, especially regarding mixed-signal, low power, 3D ICs and SIP (system-in-package).
This application space represents not longer life expectancy for nodes like 28nm and above but also a major opportunity for tools and IP providers to take advantage of existing technology to optimize it for IoT.
The name of the game in 28nm and IoT is rapid turnaround time, keeping NRE down and tracing a predictable path to getting your design done in shortest possible amount of time. That’s what the industry has to address at 28nm and going forward. These are not going to be massive chips. They are relatively smaller, but they are going to be SOCs in the truest sense of word, with custom logic, mixed signal and maybe even MEMS. They need to be done quickly and cost effectively.
There will be considerable reuse. For years, we’ve talked about the concept of platforms--large, differentiated platforms in the mega-SoC paradigm that can be retargeted. We’ll see a different incarnation of platform reuse in these more mature nodes for IoT applications.
As a side note, what’s fascinates me is that for the first time in my memory, we’ve got several nodes that are highly active at once. In the past, there was always a trailing node and leading node and a peak node. Now there is no one peak. That will continue for some time. There’s an expectation that 28nm node will be the longest life and highest volume node in the history of the industry. It certainly will be the highest volume node for IoT. It’s a mature node with excellent yields; it can handle analog mixed-signal, digital; it has lots of benefits.
We need to continue to innovate relentlessly in the core EDA space because the challenges aren’t letting up. This is where you’re seeing Cadence aggressively drive the notion and practice of “shift left.” Shift left means that steps once done later in the design flow must now start earlier. Software development needs to begin early enough to contemplate hardware changes (i.e., hardware optimization and hardware-dependent software optimization), while at the other end of the spectrum we see very early collaboration between the foundry, EDA toolmakers and IP suppliers (now system enablement companies) to “co-optimize” the value proposition of the new node.
The shift left also creates the need for faster subsystem integration and assembly along with retargeting of existing subsystems, the prototyping of new ones, along with performance, power and area (PPA) analysis.
For Cadence, we must optimize the tools and IP together so the design company can get what it needs in a single package effectively and designers can then add on their differentiation. That becomes a huge advantage for them.
Looking around the world, I like to say it’s a target-rich environment with tremendous room for innovation and entrepreneurship. All regions have opportunities to participate. And, given this is virgin territory and there are no leaders in some segments, it’s a unique opportunity for entrepreneurs in various regions. For example, what’s important for IoT is that it’s going to be a cost-per-part segment. There, the thrust will be on frugal innovation. Far greater design reuse is required. In developing parts of the world, the applications aren’t yet defined, and there’s no established leadership in this segment.
From an India perspective, we have a new government in place that is very proactive and dedicated to developing the electronics industry. For example, the “Make in India” campaign is expected to give a boost to manufacturing sector.
The government also is recognizing that IoT is the wave of the future and helping to foster an environment for enabling that design infrastructure. DEITY’s IoT Policy which encompasses manufacturing, human and technology capacity development, R&D and product creation, is testament to that.
2014 was an exciting year in electronics, and 2015 looks to be poised accelerate the trends we saw emerging. The advancements of semiconductor process technology progress on a record number of nodes and fronts. The industry’s shift left opens doors for product-development improvements of staggering proportion. Miniaturization is driving a revolution in packaging advancements that rivals that of the semiconductor foundries. The excitement over the possibilities of a highly connected world of things is sparking yet another dimension to innovation.
Keeping pace with so much innovation is a daunting task, but as engineers at Cadence and throughout the electronics design ecosystem will tell you, they’re happy to rise to the challenges.
By Jaswinder Ahuja, Corporate Vice President and Managing Director, Cadence India.