Jump in usage of System Verilog, UVM, and virtual in SoC design

At the recently concluded Mentor Graphics's conducted User to User (U2U) VLSI design conference held in Bangalore, Wally Rhines, CEO and Chairman of Mentor Graphics presented how EDA tools have transformed from simple gate level simulation to today's abstraction based virtual platforms. He finds from a study that most of the companies do not change EDA tools due to the availability of new features or tools, but more due to any disasters/failures in the designs. The reason is design methodologies are hard to change, substitution of new tools is risky, according to Wally Rhines. But isn't the innovation is all about risk-taking, and changing processes and methodologies for improvement. Do the smart project heads not calculate the cost of risk versus benefits? For some linear performance and speed benefits alone, moving from the Mentor's platform to Cadence, Synopsys, Aldec or some other vendor or vice-versa is not preferred, because it costs huge to buy a different set of EDA tools from different vendor. It is not just the cost of the EDA tool, but it is even more with time and human resources expences. In some aspects and market conditions, Wally Rhines is right. But when a team starts a new design with time to market pressure and have cash to take risk, then why not go for a new tool, if the tools help to complete the design in weeks rather than months. But the problem is mo...