Variance linked yield challenge; A tough one for the semiconductor fab experts

When the smooth ball is rolled down on an extremely smooth slope by just placing over the surface, however smooth and uniform is the slope and the ball, most of the times the ball will not stop at exactly same point. The micro forces change the ball movement each time. If this is about a physically visible thing, think about semiconductor chip manufacturing at less than 20nm, where the changes happen at atomic scale level. The variance bug is haunting the industry increasingly more from 28nm onwards. With double and triple patterning, semiconductor fabs could achieve some yield success up to 20nm . But further down at 16nm and 14nm, the difficulty level is as tough as like sending space capsule to deeper space. The consistent achievement in both fields is extremely challenging. The variation in etching/doping and depositing is not man or machine triggered. They all as per present knowledge are not falling out of line, it is happening however the best rope-walk the semiconductor fab engineers are doing. It is the big wall, which need to understood lot deeper. So basically demanding atomic control of material properties. Semiconductor manufacturing equipment vendor Lam Research has made a new equipment called 2300 Kiyo F Series conductor etch system, which Lam claims uses a breakthrough technology called the Hydra Uniformity System for cross-wafer process control t...