Open-Silicon and GLOBALFOUNDRIES together built a 2.5D chip
Open-Silicon and GLOBALFOUNDRIES have together built a functional system-on-chip (SoC) with two 28nm logic chips embedding ARM Cortex-A9 processors connected on a silicon interposer, which is called 2.5 semiconductor packaging. This 2.5 device is for mobile and low-power server applications.
The two processors are attached to a silicon interposer, which is built on a 65nm manufacturing flow with through-silicon-vias (TSVs) to enable high-bandwidth communication between the chips. This approach allows designers to choose the most appropriate process technology for each function of their SoC, while the interposer and TSVs allow for finer grain and lower power connectivity than traditional packaging solutions, leading to smaller form factors and reduced power budgets for next-generation electronic devices, says Open Silicon.
“We are now much closer to building a system in package than before and Open-Silicon is extremely pleased to be at the forefront of making 2.5D a reality with our foundry and OSAT partners,” said Dr. Shafy Eltoukhy, vice president of technology development at Open-Silicon. “Given the multitudes of advantages that this technology offers, we firmly believe that widespread adoption along with heterogeneous die-integration will ensue soon.”
“As chip designers face growing complexity and cost at smaller geometries, the adoption of 2.5D technology is increasingly being viewed as an alternative to traditional scaling at the transistor level,” said Srinivas Nori, director of SoC innovation at GLOBALFOUNDRIES. “By collaborating closely with design partners like Open-Silicon and OSAT partners like Amkor, we will be able to accelerate the availability of this technology while minimizing cost, improving yield, maximizing re-use, and decreasing risk.”
Open-Silicon shared the system features of this 2.5D having below characteristics:
Logic die including dual-core ARM Cortex-A9 CPUs, as well as DDR3, USB and AXI bridge interfaces
A special EDA reference flow designed to address the additional requirements of 2.5D design, including top-level interposer design creation and floor planning, as well as the increased complexity of using TSVs, front-side and back-side bumps, and redistribution layer (RDL) routing
Support for additional verification steps brought on by 2.5D design rules
Custom die-to-die IO for better area and power characteristics providing a maximum of 8GB/s full-duplex data-rate across the two die through the silicon interposer
A development board with memory, boot-ROM, and basic peripherals to demonstrate the die-to-die interface functionality through software running on the CPUs embedded in the logic dies
A test methodology consisting of Boundary Scan and Loopback modes
Package-related design rules, back-side integration, copper pillar micro-bumping, and 2.5D product assembly by Amkor Technology, a leading supplier of outsourced semiconductor packaging and test services
Author: Srinivasa Reddy N