Automated setup for robust testing of USB2.0 physical layer at subsys Level

In recent past consumer electronics has continuously making highlights with the introduction of new gadgets. Every week we can see in news and magazines something new related to this segment. Manufacturers try to pack the devices with more and more features, ever increasing memory space and high speed of processors with almost no compromise on power consumption figures. While on one side all these key features give an edge to products in the competitive market, on the contrary they put serious challenges to companies in order to sustain the quality and reliability of products. One such challenge being discussed in this article is related to ensure performance and reliability of high speed serial links e.g. universal serial bus 2.0 (USB2.0). In high-speed data transfer, serial links are becoming preferred choice of system designers and thus gaining more and more importance in the industry. While they do offer some of the great advantages viz. higher speed, low power, lesser cabling, easy connectivity; they also demand many system level constraints to be carefully addressed. CHALLENGES: One of the major concerns with High-Speed serial links is noise susceptibility, which can affect the performance very badly. Even if a single bit is corrupted during transmission, entire packet can be turned down by the receiver and information is lost. There may be carefully devised method...