Top VLSI design white papers at Aldec

EDA design software vendor Aldec has done an appreciable job in providing learning material and online training courses on latest technologies to VLSI design engineers. The announcement news titled "VLSI design: Free online UVM training from Aldec" we published in EE Herald is one of the most read articles in year 2013. Aldec has listed the below white papers which have received highest downloads in 2013 which are available on Aldec's website. 1. Using Plots for HDL Debugging as a Powerful Alternative to Traditional Waveforms The most commonly used approach to analyzing objects in an HDL design, is based on the well-known digital waveforms available with any commercial simulator today. Such a time domain representation of data with respect to time, allows verifying many parameters of a designed digital system, but it may not be efficient … 2. DO-254: Increasing Verification Coverage by Test Verification coverage by test is essential to satisfying the objectives of DO-254. However, verification of requirements by test during final board testing is challenging and time-consuming. This white paper explains the reasons behind these challenges, and provides recommendations how to overcome them. The recommendations … 3. Randomization and Functional Coverage in VHDL Modern digital designs reach the scale of complete systems and require support of Constrained Random...