Synopsys' Aart de Geus on effect of the fin of the FET

In semiconductor chip design and manufacturing, the power of Electronic Design Automation software is only increasing. Its not just the traditional design which includes verification, synthesis, analysis, and such normal data-compute intensive tasks, software is even playing role in error/bug/failure estimation due to minute physical variations in silicon and other semiconductor, dielectric, conductor, and insulator material used in chip fabrication. The top vendor of VLSI design software Synopsys is offering broad set of tools for nearly every task in chip design and manufacturing. This writer met with Chairman and Co-CEO of Synopsys Dr. Aart De Geus, the well-known influential person in the semiconductor industry. By Srinivas He was in Bangalore, India for the Synopsys' annual SNUG event 2013. He shared the latest trends in silicon chip industry influenced by the 3rd dimension of chip fabrication i.e. the fin of the finFET. Here are some of the points he shared on node race, semiconductor market and the VLSI design: I asked him whether the node race is soon reaching a climax? Aart De Geus: No, it is opposite — node race is accelerating again, because the semiconductor industry for fourty year(past) was using planar transistors, so there it was sort of becoming more and more difficult, but with the coming of finFET which are the vertical transist...