IEEE 1149.1-2013: Another major step in evolution of standards for chip design

The design reuse is a norm in chip design, particularly when you are designing a SoC with muticore processor. It's not easy to become first time successful in taping out silicon. The lack of standards in silicon IP has been the challenge all these years. However things are changing, where the standard for chip design are evolving. The latest in this is the announcement of IEEE 1149.1-2013 "Standard for Test Access Port and Boundary-Scan Architecture." which the VLSI industry calls as JTAG, for "Joint Test Action Group". IEEE 1149.1-2013 is meant to lower the chip design cost across the complete line of its use such as IP creation, IC design, assembly and test and system/board design. IEEE says "The revision of IEEE 1149.1, the first for the standard since 2001, allows critical domain expertise for intellectual property (IP)—how to configure a serializer/deserializer (SERDES) for loopback testing, for example—to be transferred in a computer-readable format from the IP designer to IC designers and, in turn, to designers of printed circuit boards (PCBs) and to test engineers, gradually magnifying industry cost savings along the supply chain. The cost savings for the electronics industry that IEEE 1149.1-2013 is intended to unlock are estimated to be in the billions of dollars." The Tcl based IEEE 1149.1-2013 is a hierarchical Procedural Definition Language (PDL) and is hier...