IEEE 1149.1-2013: Another major step in evolution of standards for chip design

Date: 17/06/2013
The design reuse is a norm in chip design, particularly when you are designing a SoC with muticore processor. It's not easy to become first time successful in taping out silicon. The lack of standards in silicon IP has been the challenge all these years. However things are changing, where the standard for chip design are evolving. The latest in this is the announcement of IEEE 1149.1-2013 "Standard for Test Access Port and Boundary-Scan Architecture." which the VLSI industry calls as JTAG, for "Joint Test Action Group". IEEE 1149.1-2013 is meant to lower the chip design cost across the complete line of its use such as IP creation, IC design, assembly and test and system/board design.

IEEE says "The revision of IEEE 1149.1, the first for the standard since 2001, allows critical domain expertise for intellectual property (IP)—how to configure a serializer/deserializer (SERDES) for loopback testing, for example—to be transferred in a computer-readable format from the IP designer to IC designers and, in turn, to designers of printed circuit boards (PCBs) and to test engineers, gradually magnifying industry cost savings along the supply chain. The cost savings for the electronics industry that IEEE 1149.1-2013 is intended to unlock are estimated to be in the billions of dollars."

The Tcl based IEEE 1149.1-2013 is a hierarchical Procedural Definition Language (PDL) and is hierarchical extensions to the original Boundary Scan Description Language (BSDL) to describe on-chip IP test data registers. Eight new optional IC instructions provide a foundation for configuring I/Os for board test, mitigating false failures when re-testing the IC at the board level and correlating the results back to wafer level test through an Electronic Chip ID. So finally a e-ID for the chips, which may help in preventing counterfeit ICs.

The engineer can now equipped with single way of communicating with the chip IP rather than multiple ways for different vendors.

C.J. Clark, chair of the IEEE 1149.1 working group and chief executive officer of Intellitech has put up a power point presentation in educating the chip designers the benefits of this new standard, which is available at The presentation is titled as "New IEEE Std. 1149.1-2013 lowers industry costs through test re-use from IP to Systems". IP and IC designers can transfer critical expertise to customers in English like language. He quotes "Now, for the first time in our industry, a standard overcomes the 'Tower of Babel' language differences and enables on-chip tests to be re-used and correlated across IC, board and field automatic test equipment (ATE). It's easy to see how the cost savings propagate across vendors and buyers in the IC supply chain."

IEEE 1149.1-2013 connects to IEEE 1801-2013 by supporting segmented on-chip test data registers that cross power domains specified by IEEE 1801-2013. IEEE 1149.1-2013 helps enable descriptions and operation of IP accessible via IEEE 1500-2005. IEEE 1149.1-2013 domain segmentation adds new capability to the IEEE 1500 Wrapper Serial Ports.

The need of IEEE 1149.1-2013 standards is said to be even more important for designing SoCs with complex programmable I/Os and with multiple power domains.

The new IEEE 1149.1-2013 includes structural and procedural description languages to support re-use of on-chip infrastructure IP or what Intellitech calls "Silicon Instruments." Examples of Silicon Instruments are: Memory BIST, I/O BIST, Logic BIST, SERDES PRBS, voltage droop monitors and temperature monitors. Clarke said an engineer with a low cost USB based JTAG controller from an FPGA vendor and Intellitech's NEBULA software can start communicating with a chip in the lab, or start developing 1149.1-2013 packages for his or her own IP. The freely available NEBULA product for accessing internal JTAG Silicon Instruments using 1149.1-2013 is available at Silicon Instruments.

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Author: Srinivasa Reddy N
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