Jasper and Duolog offering integrated chip design flows for IP/SoC design

Jasper Design Automation and Duolog Technologies offering integrated chip design flows to enable IP/SoC development teams to deliver qualified, integration-ready IP and SoC assembly that is seamlessly verified using formal verification methods. “ARM delivers packaged and verified IP that enables our customers to meet their design targets with reduced risk,” said John Goodenough, vice president of Design Technology and Automation, ARM. “Duolog and Jasper have been valued partners providing IP integration and verification tools and flows for these mission-critical processes. The new, integrated flows from the two companies should both increase productivity and quality for us and for our customers.” The partnership will initially deliver two flows. The first will focus on the capture and verification of register metadata, combining Duolog’s Socrates Bitwise register management tool with the JasperGold Control and Status Register (JG-CSR) Verification App. The flow will enable IP designers to verify both executable specifications and RTL for consistency and completeness. The second flow leverages Duolog’s Socrates Weaver SoC integration tool and the JasperGold Connectivity Verification App (JG-CONN). This flow will enable SoC design teams to assemble, construct and exhaustively verify a complete SoC integration, including temporal and conditional connections, as well as...