Working test chip features Tensilica IP core made using GLOBALFOUNDRIES super LP tech

Technische Universität (TU) Dresden has successfully operated a low-power test-chip featuring a Tensilica Xtensa LX4 DSP equipped with RacyICs power management IP implemented in GLOBALFOUNDRIES’ advanced 28nm Super Low Power (SLP) technology. The chip is able to operate in a wide voltage and frequency range from 0.7V to 1.1V and 90 MHz to 1 GHz. Within that range, the optimal voltage/frequency combination is determined adaptively based on a new hardware performance monitor concept. The complete baseline IP (standard cell libraries, IO cells, SRAM blocks, PLL) was developed by the university team, who also did logic synthesis, place and route and sign-off of the test-chip. “Our ability to successfully realize microchips in advanced technologies is a result of a long- term strategy to build an experienced team, which covers all aspects of analog, digital and mixed-signal IC design.” stated Professor René Schüffny, TU Dresden. “This accumulated engineering competence is one key enabler for TU Dresden’s leading-edge research in the field of complex systems based on advanced electronics.” The chip has been developed within the frame of the CoolRF28 project. This project is part of the Leading-Edge Cluster “Cool Silicon”, which is sponsored by the German Federal Ministry of Education and Research (BMBF) within the scope of its Leading-Edge Cluster Competition. In the “Cool Sili...