STATS ChipPAC and UMC demo 3D test IC under open ecosystem collaboration

Semiconductor packaging expert STATS ChipPAC and the semiconductor foundry service provider United Microelectronics Corporation have demonstrated TSV-enabled 3D IC chip stacking technology developed under an open ecosystem collaboration. I/O memory test chip stacked over TSV-embedded 28nm processor test chip is assessed for package-level reliability. This demonstration is to tell the market that reliable 3D IC manufacturing is offered jointly by UMC’s foundry and STATS ChipPAC’s packaging services. ”The next level of chip integration is rapidly evolving, and 3D IC technology is poised to enable the next frontier of IC capabilities for customers under various deployment models.” said Shim Il Kwon, VP of Technology Innovation of STATS ChipPAC, “The open ecosystem collaborative approach drives proven and reliable 3D IC solutions for the semiconductor market by combining the foundry partner’s robust, leading-edge TSV and front-end-of-line (FEOL) process technologies in a complementary platform with an Outsourced Semiconductor Assembly and Test (OSAT) service provider with innovative engineering excellence to seamlessly integrate mid-end-of-line (MEOL) and back-end-of-line (BEOL) 3D IC processes. We are pleased with UMC’s commitment to this role and look forward to future collaborations. The results are a proven solution platform that will enable customers to capitalize on new m...