Latest Virtuoso from Cadence for 20nm SoC chip design prevent bug creation

Cadence Design Systems has made available of its Virtuoso Advanced Node VLSI design software with custom/analog chip design capabilities supporting the semiconductor fab nodes of 20 nm and below. Virtuoso Advanced Node takes care of preventing errors/bugs before they are created rather than detect them late in the design process so saving time in debugging. This software along with Cadence Encounter RTL-to-GDSII flow, QRC Extraction and Physical Verification System, Virtuoso Advanced Node makes-up much of the VLSI chip design platform for deeper nodes. Smart Phone Cadence says the new Virtuoso Advanced Node environment uses a novel color-aware layout approach to tackle 20- and 14-nanometer designs. The deep node SoC chip design challenges such as layout-dependent effects (LDEs), double patterning, color-aware layout and new routing layers are taken care in this latest version. Cadence says Virtuoso integrate seamlessly with the Cadence Integrated Physical Verification System (IPVS) used for signoff DRC and DPT checking — to conduct on-the-fly checks that reduce layout iterations. STMicroelectronics has praised this tools, here is the quote by Pierre Dautriche, senior director at STMicroelectronics: “As a semiconductor leader, we have moved aggressively to meet the new complexities of 20-nanometer technology to stay on the cutting edge of design. The new Virtuoso ...