Latest Virtuoso from Cadence for 20nm SoC chip design prevent bug creation
Date: 28/01/2012
Cadence Design Systems has made available of its Virtuoso Advanced Node VLSI design software with custom/analog chip design capabilities supporting the semiconductor fab nodes of 20 nm and below. Virtuoso Advanced Node takes care of preventing errors/bugs before they are created rather than detect them late in the design process so saving time in debugging. This software along with Cadence Encounter RTL-to-GDSII flow, QRC Extraction and Physical Verification System, Virtuoso Advanced Node makes-up much of the VLSI chip design platform for deeper nodes.
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Cadence says the new Virtuoso Advanced Node environment uses a novel color-aware layout approach to tackle 20- and 14-nanometer designs.
The deep node SoC chip design challenges such as layout-dependent effects (LDEs), double patterning, color-aware layout and new routing layers are taken care in this latest version. Cadence says Virtuoso integrate seamlessly with the Cadence Integrated Physical Verification System (IPVS) used for signoff DRC and DPT checking — to conduct on-the-fly checks that reduce layout iterations.
STMicroelectronics has praised this tools, here is the quote by Pierre Dautriche, senior director at STMicroelectronics:
“As a semiconductor leader, we have moved aggressively to meet the new complexities of 20-nanometer technology to stay on the cutting edge of design. The new Virtuoso advanced-node capabilities have contributed to our transition by providing high-quality automation for our custom/analog chips. Virtuoso Advanced Node takes into account the idiosyncrasies of designing at 20 nanometers and ensures a much more efficient development cycle.”
Features and Capabilities as stated in the release by Cadence:
LDE analysis using incremental layout — Virtuoso Advanced Node enables engineers to build their physical design and check it as they go, to ensure they are making the right choice at each step, rather than having to wait until the end. It delivers novel technology that helps decrease costly design iterations by allowing designers the ability to use partially completed layout as part of the LDE analysis, detecting layout-dependent effects at the earliest moment in the design cycle. LDEs — such as stress effects, poly and diffusion spacing/length, well proximity effects, and parasitics -- are handled with detailed test benches that analyze multiple corners to ensure that the circuit will function as specified.
When this technique is combined with Cadence MODGENs and constraints, IPVS and final hotspot detection and correction with Virtuoso DFM, users can expect up to a 30 percent improvement in their overall verification time. By methodically building and checking the design, the designer should eliminate massive “rip ups” and “reroutes” that can be found at the end if the circuit wasn’t checked along the way.
Double patterning and color-aware layout — Double patterning, a manufacturing requirement at 20 nanometers, splits the design layers into two masks, separating structures that are too close together. But double patterning brings “coloring” challenges to designers. Virtuoso Advanced Node delivers real-time automated color-aware, design-rule-driven layout to enable the creation of area-optimized layout. It provides engineers the ability to match, lock and store colors on critical nets and geometries (through schematic constraints or directly on the layout), and to identify, debug and fix errors as they go, rather than later in the design process, when they are more difficult to fix.
New routing layers — Foundries require the utilization of new local interconnect (LI) layers, or middle-of-line (MOL) layers, that are used to create densely packed routes inside complex devices. These layers have restricted design rules governing local interconnect and the vias that are used with them, presenting the challenge of maintaining signal integrity from pin to pin of the transistors. Virtuoso Advanced Node technology provides a local interconnect-aware wire editor and router that address the issue of complex LI rules.
Developed specifically for the most cutting-edge designs, the Virtuoso Advanced Node options do not replace the industry-leading 6.x version of the Virtuoso technology, which targets mature and mainstream geometries, and which will continue to be enhanced by Cadence.
Virtuoso reduces and eliminates tasks that would make 20-nanometer design much more time consuming and labor intensive, as per Dr. Chi-Ping Hsu, senior vice president, Silicon Realization Group at Cadence
