Date: 27/01/2013

Open-Silicon does backbone SoC interconnect using Arteris' FlexNoC IP

Arteris has announced that Open-Silicon implemented the Arteris FlexNoC interconnect IP as the backbone SoC interconnect in a high-performance ARM-based networking SoC design.

“We were able to close timing in a fraction of the schedule needed previously for designs using older crossbar-based architectures. We used the Arteris FlexNoC interconnect IP within our Center of Excellence for ARM Technology to optimize power consumption and performance for an ARM-based subsystem,” said Colin Baldwin, senior director of marketing, Open-Silicon. “Arteris’ network-on-chip interconnect IP made timing closure much easier and allowed us to implement the QoS management required for the design’s high-performance I/O and sophisticated hardware acceleration engines. In addition, we were able to close timing in a fraction of the schedule needed previously for designs using older crossbar-based architectures.”

“Arteris is excited that the ARM Technology Center of Excellence at Open-Silicon has chosen Arteris FlexNoC to meet the needs of its most demanding SoC customers,” said K. Charles Janac, President and CEO of Arteris. “Arteris NoC technology eases timing closure and enables SoC designers to complete their projects in a fraction of time compared to older technologies.”
Author: Srinivasa Reddy N