Imec and Cadence tested automated DFT for 3D Memory-on-Logic Ics

imec and Cadence Design Systems have announced that they together developed, implemented and validated an automated 3D Design-for-Test (DFT) solution to test logic-memory interconnects in 3D semiconductor IC packaging of DRAM and logic silicon dies. Using Cadence Encounter tool from Cadence the team has verified an industrial test chip containing a logic die and a JEDEC-compliant Wide-I/O Mobile DRAM. Imec explains the design of the test chip is an interposer-based 3D stacked chip which includes a silicon interposer base die, a 94mm2 logic system-on-chip in 40nm technology, and a single Wide-I/O DRAM rank. The silicon area of the additional DFT wrapper is negligible compared to the total logic die size (<0.03%), based on the test. Tens of patterns were generated in only a few seconds with 100% coverage of the targeted faults, says imec . All 3D-DFT logic in the logic die was automatically inserted with Cadence Encounter RTL Compiler while the Interconnect test patterns were generated with Encounter Test ATPG, according to imec. As per the latest standards from JEDEC(JESD-229) for stackable Wide-I/O mobile dynamic random access memories (DRAMs) specifying the logic-memory interface boundary scan features has to facilitate interconnect testing. Imec and Cadence offer design-for-test (DFT) architecture and corresponding automatic test pattern generation (ATPG) approach by su...