Date: 25/10/2012

Synopsys' 3D chip design tools supports TSMC’s CoWoS reference flow

Synopsys, Inc. has announced that it is delivering a comprehensive 3D-IC design solution that is included in TSMC's CoWoS (Chip on Wafer on Substrate) Reference Flow. The design flow is the result of the latest collaboration between the companies on 3D-IC integration technologies. It offers a smooth transition from a traditional "2D" integrated circuit (IC) to a multi-die stacking design flow. In support of the TSMC CoWoS reference flow, Synopsys has released enhanced versions of its Galaxy Implementation Platform tools for physical implementation, parasitic extraction, physical verification and timing analysis. With the new flow and tool enhancements, engineers can improve productivity, lessen time-to-market and speed time-to-volume when designing multi-die systems for TSMC CoWoS silicon.

"3D-IC integration technologies offer tangible benefits for design teams looking to deliver extreme performance, the smallest form factor, and the lowest power consumption," said John Chilton, senior vice president of marketing and corporate development at Synopsys. "3D-IC integration is proving to be key to extending the lifespan of established semiconductor processes and enabling the integration of heterogeneous technologies, complementing traditional 'Moore's Law' transistor scaling for many application domains. Synopsys' contributions to the TSMC CoWoS Reference Flow enable designers to quickly realize innovative and advanced multi-die systems."

"TSMC and Synopsys have a long-term collaboration on design flows," said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. "The combination of Synopsys EDA tools with TSMC CoWoS technology provides designers with a productive answer for manufacturability of multi-die systems that optimize performance and power consumption."

Synopsys' Galaxy Implementation Platform features support for TSMC's CoWoS reference flow and technology. TSMC has validated Synopsys' implementation, analysis and signoff tools, including:

Physical implementation:
1. IC Compiler multi-die physical implementation with support for placement, assignment and routing of microbump, thru-silicon via (TSV), probe-pad and C4; combo bump cells allowing simplified and flexible bump assignment; microbump alignment checks; redistribution layer (RDL) and signal routing, and power mesh creation on CoWoS interconnection layers

Analysis and signoff:
1. Hercules layout vs. schematic (LVS) connectivity checking between stacked die
2. StarRC Ultra parasitic extraction support for TSV, microbump, RDL and signal routing metal for CoWoS design interconnection
3. PrimeTime timing analysis of multi-die systems

Synopsys' 3D-IC solution is currently in limited customer availability.

Source: Synopsys
Author: Srinivasa Reddy N