ISO 26262 and ISO/SAE 21434 compliant compilers support Andes FuSa certified RISC-V IP
Date: 31/03/2024
TASKING has recently expanded its RISC-V tool suite to include support for the Andes FuSa certified RISC-V IP, complying with ISO 26262 for functional safety and ISO/SAE 21434 for cybersecurity. This advancement aims to provide a comprehensive solution for automotive systems development, offering a range of tools for compilation, debugging, performance tuning, timing, and coverage analysis.
The newly introduced RISC-V compiler is compliant with ASIL D standards and seamlessly supports both current and future FuSa certified Andes RISC-V cores.
Adaptability: The compiler is designed to adapt to the RISC-V ISA and its extensions, including Andes-specific extensions, ensuring dynamic optimization tailored to the target device for enhanced efficiency and performance.
Andes Technology has made significant strides in the automotive market with the introduction of the world's first RISC-V ISO-26262 fully compliant core, N25F-SE, and is set to unveil the ASIL-B certified D25F-SE with RISC-V SIMD/DSP P-extension support.
Andes plans to launch processors meeting the ASIL-D standard, including the compact and secure D23-SE, high-performance D45-SE, and an ADAS-capable core in the AX60 Series, showcasing tailored solutions for diverse automotive applications.
The collaboration between TASKING and Andes aims to expedite development processes in the automotive industry, enhancing the performance and robustness of safety-critical RISC-V applications.
“AndesCore RISC-V IP, certified with ISO 26262, presents a solid portfolio of automotive processor solution offering unparalleled level of flexibility and efficiency benefits to silicon development,” said Samuel Chiang, Deputy Marketing Director of Andes, “Our partnership with Tasking enables customers in the automotive industry to expedite their development processes, enhancing the performance and robustness of safety-critical RISC-V applications.”
Commenting on the collaboration, Gerard Vink, TASKING’s RISC-V lead, expressed enthusiasm, stating, “We are thrilled to collaborate with Andes and their ecosystem partners. The seamless interoperability of our tools with Andes RISC-V IP across development platforms ranging from virtual prototype to silicon implementations underscores our commitment to providing comprehensive lifecycle support for SoC development teams. Leveraging TASKING’s advanced FuSa and Cybersecurity processes, our users can fast-track compliance efforts, accelerating the time-to-market of RISC-V based automotive software solutions.”
TASKING to present its latest tools for the development of high-performance, safe and secure embedded automotive software at embedded world 2024 in Nuremberg from April 9 to 11, 2024. At booth 255 in hall 4, TASKING will be presenting its wide range of tools that span the complete software development process, known as “Compile, Debug, Analyze”. TASKING' Workstation 3 to highlight RISC-V tool support. The RISC-V tools enable compilation, verification, debugging, performance tuning, timing analysis, and coverage analysis for software running on multi-core, multi-hart SoCs. The tools are demonstrated using Andes' ISO 26262-certified RISC V processor Ips and associated MachineWare Virtual Models. This demo will also be shown at the upcoming Andes RISC V Conferences in Taiwan, China and Japan.
