Generative AI EDA tool Cadence Voltus InsightAI to automatically fix EM-IR violations
Date: 06/11/2023
Cadence announces a new generative AI EDA tool called Voltus InsightAI to automatically identify the root cause of EM-IR drop violations early in the semiconductor chip design process and selects and implements the most efficient fixes to improve power, performance, and area (PPA) of deep node chips and chiplets.
This AI tool Voltus InsightAI uses machine learning-generated power grid models for faster IR inferencing within complex VLSI design implementation. PPA improvement is achieved due to its early IR drop prediction and prevention capabilities and save from any excessive power grid design.
Cadence claims VLSI semiconductor chip designers can fix up to 95% of violations prior to signoff, leading to a 2X productivity improvement in EM-IR closure.
At advanced nodes such as 5 nm, 3 nm and further deeper nodes power integrity (PI) is a major design challenge with significant number of EM-IR violations at signoff, and due to exploding design data-size requires huge computing resources. Voltus InsightAI is designed to address these challenges where it uses breakthrough machine learning methods for very fast incremental IR analysis.
Chip designers can use this tool not only to design monolithic chip development but also in heterogeneous 3D IC specific chiplet power integrity analysis.
Cadence lists these below features in its release:
Fast IR Inferencing Engine: The solution uses proprietary neural networks to build models of the power grid and can perform extremely fast incremental IR analysis to provide instant feedback on the impact of design changes.
IR Drop Diagnostics: Voltus InsightAI uses deep learning to discover the root cause of IR drop problems and can quickly identify aggressors, victims and resistance bottlenecks. It uses electrical, spatial and timing factors for predicting IR drop issues during design.
Multi-Method Fixing: Decision-tree methods are utilized to perform timing and design rule check (DRC)-aware fixes of IR drop, using multiple methods like placement, grid reinforcement, routing and engineering change orders (ECOs). Voltus InsightAI selects precise fixing methods based on the root cause of the problem, driving better utilization and improved PPA.
Fully Integrated Solution: Voltus InsightAI is fully integrated with Cadence’s solutions, including the Cadence Innovus Implementation System, the Cadence Tempus Timing Solution, the Cadence Voltus IC Power Integrity Solution, and the Cadence Pegasus Verification System for complete IR design closure from implementation to signoff? that is timing- and DRC-aware.
“As we move to more advanced nodes, EM-IR is quickly becoming one of the most pressing challenges, requiring novel and innovative approaches to address customer needs. With Voltus InsightAI, Cadence has pioneered applying generative AI technology to EM-IR, focusing not just on signoff, but early detection and prevention of EM-IR violations as well,” said Ben Gu, Corporate Vice President of R&D, Multiphysics Systems Analysis Business Unit, Cadence. “With this capability, designers don’t need to over-design the power grid, thereby enabling far better PPA. Customers are seeing impressive results as they can leverage this breakthrough technology to fix up to 95% of violations prior to signoff and achieve more than 2X productivity improvement in EM-IR closure.”
More details on this product can be found at: www.cadence.com/go/VoltusInsightAI
Here below are the comments made on this AI EDA tool by executives working in semiconductor chip design industry:
Berkan Baran, vice president of implementation, Solutions Engineering Group, Arm said “As the provider of foundational technology, reducing complexities of power integrity on advanced nodes is critical in ensuring we can continue to meet performance requirements of the next era of computing. Said. We are enthusiastic about the initial results of our evaluation of the Cadence Voltus InsightAI technology on a 3nm Arm Cortex-X4 core block and we look forward to continuing our work with Cadence on this technology to help close the power integrity gap on advanced nodes.”
Jon Stahl, Senior Director of ASIC Development, Cisco (Acacia) commented “We have evaluated the new Cadence Voltus InsightAI and see promise in the technology to fix IR drop violations. The tool was automatically able to fix a significant number of violations in a very efficient manner. We are working with Cadence to deploy it for future projects.”
CC Mao, Deputy General Manager, Computing and Artificial Intelligence Technology Group, MediaTek quoted “As one of the world’s leading semiconductor companies, MediaTek must push the boundaries of chip design, and we need highly advanced software solutions to help us achieve our aggressive time-to-market goals. Using the new Cadence Voltus InsightAI technology, we have seen a 65 – 70% reduction in IR drop violations at the block level, and designs were optimized using both vector-based and vectorless flows.”
