Generative AI EDA tool Cadence Voltus InsightAI to automatically fix EM-IR violations

Cadence announces a new generative AI EDA tool called Voltus InsightAI to automatically identify the root cause of EM-IR drop violations early in the semiconductor chip design process and selects and implements the most efficient fixes to improve power, performance, and area (PPA) of deep node chips and chiplets. This AI tool Voltus InsightAI uses machine learning-generated power grid models for faster IR inferencing within complex VLSI design implementation. PPA improvement is achieved due to its early IR drop prediction and prevention capabilities and save from any excessive power grid design. Cadence claims VLSI semiconductor chip designers can fix up to 95% of violations prior to signoff, leading to a 2X productivity improvement in EM-IR closure. At advanced nodes such as 5 nm, 3 nm and further deeper nodes power integrity (PI) is a major design challenge with significant number of EM-IR violations at signoff, and due to exploding design data-size requires huge computing resources. Voltus InsightAI is designed to address these challenges where it uses breakthrough machine learning methods for very fast incremental IR analysis. Chip designers can use this tool not only to design monolithic chip development but also in heterogeneous 3D IC specific chiplet power integrity analysis. Cadence lists these below features in its release: Fast IR Inferencing En...