Tessent RTL Pro to streamline and accelerate chip design DFT processes
Date: 11/10/2023
Tessent RTL Pro, an innovative software solution developed to assist integrated circuit (IC) design teams in streamlining and accelerating a wide range of crucial design-for-test (DFT) processes for their next-generation designs, was unveiled by Siemens Digital Industries Software.
Engineers must recognize and handle testability challenges at the earliest feasible phases of design as IC designs continue to increase in size and complexity. Siemens Tessent software enables customers to handle this need, by allowing them to analyse and insert most of DFT logic early in the design process, perform rapid synthesis and generate ATPG automated test patterns for identifying and addressing outliers so that suitable actions can be taken.
In order to facilitate a pioneering capability within the industry, the novel solution seamlessly incorporates Siemens' highly acclaimed Tessent DFT tools. Tessent RTL Pro analyses RTL complexity and adaptability for test point insertion, determining whether the customer's RTL structure can be edited efficiently, which is important when inserting test points throughout the design. This new feature can assist customers in reducing design turnaround time and improving time-to-market.
. "Adopting Tessent RTL Pro for our next-generation automotive semiconductor design allows us to extend our shift-left strategy and reduce the iterations of the conventional design flow. This is all possible while maintaining our best-in-class coverage and pattern count," said Tatsuya Saito.
Tessent RTL Pro's "shift-left" technology significantly improves the ability of third-party tools to maximize area and timing when adding DFT logic prior to synthesis, leaving only the scan insertion for the gate level. Design insertion occurs throughout the RTL development stage, with RTL output allowing for coherent integration with third-party synthesis and verification software. Furthermore, RTL Pro generates design files that may be used with any downstream synthesis or verification flows, eliminating the need for a closed-flow procedure.
Tatsuya Saito, Senior principal EDA engineer, Digital Design Technology Department, Shared R&D EDA Division Renesas Electronics Corporation said “The ability to provide our back-end and verification teams with the same, complete design view containing all Tessent IP, including VersaPoint test points in RTL, is paramount for our competitiveness."
“Tessent RTL Pro continues Siemens’ drive to provide the industry’s most advanced solutions to chip designers and DFT engineers for their design flows,” said Ankur Gupta, vice president and general manager, Tessent division, Siemens Digital Industries Software. “With the ability to analyse and insert wrapper cells, x-bounding logic, and VersaPoint test points at the RTL stage of design, customers can now extend their shift-left initiatives by substantially enhancing the testability of their designs."
For more information on Tessent RTL Pro andSiemens EDA's comprehensive suite of IC design solutions visit:www.siemens.com/tessent
News Source: Siemens EDA
