Applied's new deposition, CMP, CVD, PVD, and PECVD semiconductor equipments for 3D chips
Date: 11/07/2023
Applied Materials introduced below new semiconductor manufacturing gear for advanced 2.5 and 3 dimensional semiconductor packages.
1. The Insepra SiCN deposition system to deposit new silicon carbon nitride (SiCN) material for achieving higher dielectric bonding strength enabling structural stability and increase copper-to-copper interconnect density in the chip.
2. The Catalyst CMP solution with feature to better control the amount of “dishing,” the intentional recessing of copper material on two surfaces that will be bonded in a subsequent high-temperature annealing step. CMP dishing can create unwanted metal loss at the top surfaces of the copper pads, which can cause air gaps that decrease the fidelity and strength of the copper-to-copper bonds. Applied’s Catalyst solution is a dynamic temperature control technique that reduces dishing and increases throughput.
3. A new CVD process supporting Producer InVia 2 CVD System allows to make dielectric liners uniform and electrically robust at the extreme aspect ratios needed by logic and memory customers in a growing variety of TSV applications. The InVia 2 system uses a propriety in-situ deposition process which enables excellent conformality for high-aspect-ratio TSVs. The system also offers higher throughput than ALD technologies, thereby reducing the per-wafer cost of TSV to help further expand its adoption.
4. The Endura Ventura 2 PVD System extends its widely adopted predecessor to TSV applications with aspect ratios of up to 20:1. The Ventura 2 system increases the control of metal TSV wire deposition to ensure a complete fill that delivers high electrical performance and reliability. The new TSV PVD process has been co-optimized for use with the Producer InVia 2 CVD process, giving customers a ready solution to their most challenging TSV designs. The Ventura 2 system is being deployed by all advanced foundry/logic chipmakers and all major DRAM producers.
5. The latest generation of Applied’s Producer Avila PECVD System is designed for TSV “reveal” applications. In the TSV process flow, wafers are bonded to temporary glass or silicon carriers and then thinned using CMP and etching to make the TSVs accessible. Following the TSV reveal steps, plasma-enhanced CVD technology is used to deposit a thin dielectric layer that electrically isolates the TSVs from each other. If the PECVD process generates heat above approximately 200 Deg C, the delicate temporary bonding adhesive can be damaged, resulting in costly wafer yield loss. Applied’s Producer Avila PECVD system creates high-quality dielectric films at ultra-low temperatures and at high speed, meeting the low thermal budgets and high productivity required for TSV quality and cost.
“Heterogeneous integration is growing rapidly because it helps chip and systems companies overcome the limits of classic 2D scaling, which no longer delivers simultaneous improvements in performance, power and cost,” said Dr. Sundar Ramamurthy, Group Vice President and General Manager of HI, ICAPS and Epitaxy, Semiconductor Products Group at Applied Materials. “Our latest HI solutions advance the industry’s newest ways to pack more transistors and wiring in 2.5D and 3D configurations to increase system performance, reduce power consumption, minimize size and speed time to market.”
