Intel launched Agilex 7 with R-Tile, First FPGA with PCIe 5.0 and CXL interface
Date: 07/06/2023
Intel takes lead in high performance FPGA market over AMD Xilinx by offering chiplet based Agilex 7 heterogenous integrated multi-silicon die FPGA family with unmatchable performance for high-performance computing applications.
The two high-speed data interface features PCIe 5.0 and CXL in Agilex 7 are first in the high performance FPGA market and these are hardened Ips. These interfaces are provided through a chiplet called R-Tile. R-Tile has hard IP blocks and soft IP code for PCIe 5.0 x16 and CXL 1.1/2.0 The chiplet is connected to FPGA fabric using Intel’s embedded multi-die interconnect bridge (EMIB) technology.
Agilex 7 FPGA-fabric is made using Intel's 10 nm SuperFin technology offering high-density of logic blocks. Intel claims FPGA fabric in Agilex 7 offers high performance per Watt compared to competing 7 nm FPGAs, which is mainly AMD Xilinx. Agilex 7 embeds transceivers up to 116 Gbps. Agilex 7 is available in three series namely you F-Series, I Series and M-series.
F-Series are general purpose FPGAs with transceivers up to 58 Gbps with advanced DSP blocks such as Hardened BFLOAT16 delivering 25 TFLOPS of digital signal processing performance and crypto blocks hardened 200G (Half Duplex) crypto cores supporting AES-GCM encryption/decryption, MACsec IP to secure network traffic. Though this family does not include PCIe 5.0 and CXL it comes with PCIe 4.0 and 400 Gb Ethernet.
Learn more about this at:
https://www.intel.com/content/www/us/en/products/details/fpga/agilex/7/f-series/products.html
I Series comes with highest performance I/O interfaces PCIe 5.0 support, and cache- and memory-coherent attach to processors with Compute Express Link (CXL). This family features such as: Configurable networking support including hard Ethernet media access control (MAC), physical coding sublayer (PCS), and forward error correction (FEC) for up to 400GE.
Learn more about this at: https://www.intel.com/content/www/us/en/products/details/fpga/agilex/7/i-series.html
The M-series with the 3.9 million logic elements offer logic density as well as support memory intensive applications by featuring hardened memory OC supporting industries are used memory bandwidth at over 1 TBps using HBM2e and DDR5. M-Series FPGA packs HBM2e memory, support for LPDDR5, DDR5, and DDR4 memory. M-Series FPGA can be connected to Intel Xeon Scalable processors over the PCIe 5.0 bus or use Compute Express Link (CXL) protocol for achieving higher I/O performance in moving compute workloads between CPU and FPGA.
You can learn more on the M-series at:
https://www.intel.com/content/www/us/en/products/details/fpga/agilex/7/m-series.html
Intel said its Agilex 7 with the R-Tile chiplet is shipping production-qualified devices in volume.
“Customers are demanding cutting-edge technology that offers the scalability and customization needed to not only efficiently manage current workloads, but also pivot capabilities and functions as their needs evolve. Our Agilex products offer the programmable innovation with the speed, power and capabilities our customers need while providing flexibility and resilience for the future. For example, customers are leveraging R-Tile, with PCIe Gen 5 and CXL, to accelerate software and data analytics, cutting the processing time from hours to minutes.” –Shannon Poulin, Intel corporate vice president and general manager of the Programmable Solutions Group
Intel stated in its release "Agilex 7 FPGAs with the R-Tile chiplet deliver leading technology capabilities with 2-times faster PCIe 5.0 bandwidth as well as 4-times higher CXL bandwidth per port when compared to other competitive FPGA products. According to a white paper from Meta and the University of Michigan, adding FPGAs with CXL memory to 4th Gen Xeon-based servers while using transparent page placement’s (TPP) efficient page placement improves Linux performance by up to 18%. Additionally, UnifabriX demonstrated its CXL-enabled Smart Memory Node on multiple performance benchmarks, with one showing a 28% increase in the HPCG (high-performance conjugate gradient) benchmark score while utilizing 2-times more 4th Gen Xeon cores for HPC workloads."
