Intel launched Agilex 7 with R-Tile, First FPGA with PCIe 5.0 and CXL interface

Intel takes lead in high performance FPGA market over AMD Xilinx by offering chiplet based Agilex 7 heterogenous integrated multi-silicon die FPGA family with unmatchable performance for high-performance computing applications. The two high-speed data interface features PCIe 5.0 and CXL in Agilex 7 are first in the high performance FPGA market and these are hardened Ips. These interfaces are provided through a chiplet called R-Tile. R-Tile has hard IP blocks and soft IP code for PCIe 5.0 x16 and CXL 1.1/2.0 The chiplet is connected to FPGA fabric using Intel’s embedded multi-die interconnect bridge (EMIB) technology. Agilex 7 FPGA-fabric is made using Intel's 10 nm SuperFin technology offering high-density of logic blocks. Intel claims FPGA fabric in Agilex 7 offers high performance per Watt compared to competing 7 nm FPGAs, which is mainly AMD Xilinx. Agilex 7 embeds transceivers up to 116 Gbps. Agilex 7 is available in three series namely you F-Series, I Series and M-series. F-Series are general purpose FPGAs with transceivers up to 58 Gbps with advanced DSP blocks such as Hardened BFLOAT16 delivering 25 TFLOPS of digital signal processing performance and crypto blocks hardened 200G (Half Duplex) crypto cores supporting AES-GCM encryption/decryption, MACsec IP to secure network traffic. Though this family does not include PCIe 5.0 and CXL it comes with PCIe 4.0...