Deep node VLSI: Tool automatically adds interconnect pipelines to close timing

In deep node VLSI design using FinFETs, the transistors are getting faster, whereas the interconnect signal gets comparatively slower, that's why on-chip interconnect is topping the timing closure issues, causing delay in total SOC turnaround design time. To solve this issue in early-stage, the VLSI interconnect technology IP expert Arteris announced PIANO 2.0, an automated interconnect timing closure technology. Based on the VLSI designer experience with FlexNoC, Physical Arteris has built PIANO 2.0 to automate interconnect timing closure for both cache coherent and non-coherent subsystems. At FinFET based deep nodes starting from 28nm to 10nm /7 nm, VLSI engineers solve the issues by manually inserting pipeline stages in the chip netlist through an engineering change order (ECO) process. This new technology introduces the concept of physical interconnect distance to customers using Arteris FlexNoC and Ncore interconnect products. By using the data such as length of individual interconnect links and traces and process and performance targets, this tool calculates and automatically adds interconnect pipelines to close timing. PIANO validate this timing closure scheme with the physical synthesis capabilities of the Synopsys or Cadence EDA tools. The advantages of PIANO 2.0 includes, interconnect timing can be closed in as little as 24 hours, reduces interconnect area...