Flexible configurable cache coherent tech Ncore from Arteris

At 14 or 16 nm node and at further deeper nodes there is a huge challenge to interconnect complex subsystems on the chip. Take the example of Xilinx 3D FPGA, it packs 19 billion transistors on a chip manufactured using 20nm node, you need a extremely smart interconnect to connect multiple processors and other accelerators in these devices. The multi-storey metal layers on these highly integrated chips have grown too tall to manage them, making a fabrication with plain old interconnect technology near impossible. Through a microscope they look similar to a tall building structure. Serial bus is essential and acts like a network inside the chip. The interconnect network inside the chip works much like the wired ethernet like computer-network. When you have a multicore processors of heterogenous type on a single chip making them access cache memory with coherency is big challenge. It is required for processors with the different instruction set architecture to coherently share data in cache memory. If you ask what are the applications for such heterogenous processor core SOC chips, they include advanced driver assistance systems in autonomous cars, and many such machine vision demanding applications. NXP Semiconductors is using Ncore interconnect IP in its microcontrollers for automotive applications. Some of the other applications suggested includes high-def...