20x faster time-based RTL power analysis by Cadence

VLSI chip designer can now analyze power consumption accurately during design exploration by using Cadence Joules RTL Power Solution. This new register-transfer level (RTL) power analysis software churn out the data 20X faster using time-based RTL power analysis tech compared to other methods, claims Cadence. Joules RTL Power Solution handles up to 20 million instances overnight with gate-level accuracy within 15 percent of final power as signed off in the Cadence Voltus IC Power Integrity Solution. Joules RTL Power Solution integrates seamlessly with the Cadence Palladium emulation platform and the Stratus High-Level Synthesis (HLS) platform for early system-level power analysis and optimization. Key highlights of the Joules RTL Power Solution as shared by Cadence: Accurate RTL power estimation—The Joules RTL Power Solution performs an ultra-fast design synthesis using a new integrated prototype mode of the Genus Synthesis Solution, including physically aware clock tree and datapath buffering, and enabling accurate RTL power estimation. Multi-threaded frame-based architecture—Power analysis is parallelized across multiple CPUs accelerating in-depth power exploration. Multiple stimulus files can be analyzed simultaneously and each stimulus file can be time-sliced into frames to enable time-based power reporting. Adjustable power analysis resolution—User-selectab...