Version 6 of SoC VLSI design debugging tools from Concept

Concept Engineering to demonstrate version 6 of the company′s Vision product line to designers of analog, digital, mixed-signal circuits, systems-on-chip (SoCs), and field-programmable gate arrays (FPGAs) at the 52nd Design Automation Conference (DAC) in San Francisco, California, in June 2015. Concept's product line includes 1. StarVision PRO: analog, digital and mixed-signal debugging capabilities, customizable design rule checks and automated netlist pruning, 2. RTLvision PRO:RTL debugging and intellectual property (IP) development, 3. GateVision PRO:netlist debugging of complex SoC netlists, 4. SpiceVision PRO: exploration and debugging features for transistor-level and post-layout netlists. "With version 6, we continue to improve our specialized product family with individual tools for specific circuit debugging problems," said Pascal Bolzhauser, product manager for Concept Engineering′s Vision product line. "We have made specific enhancements to each tool and we also have incorporated multiple general usability improvements.". The enhanced features in the ver. 6 platform as explained by Concept are: 1. Improved netlist pruning: In addition to Verilog and SPICE netlist export and pruning, StarVision PRO now also allows netlist pruning for the most common post-layout formats, DSPF and SPEF. 2. Advanced post-layout debugging: Improved visualizatio...