ARM Artisan physical IP for UMC's 55 ULP

ARM simplified design of SOC chips for low-power applications using UMC's 55 nm semiconductor chip manufacturing process. ARM has partnered with UMC in offering ARM Artisan physical IP solution on 55nm. UMC 55 nm ultra-low-power process is gaining some level of popularity for development of embedded systems and Internet of Things (IoT) applications. 55 nm, being a well established and less expensive node, serves many of the popular applications in IOT. UMC 55 nm ultra-low-power process supports features such as thick gate oxide, multi-channel library options so that power consumption can be minimised in SOCs for IoT applications. "A complete physical IP foundation platform at UMC's 55ULP process technology is vital in enabling low-power and cost-sensitive designs for emerging IoT applications," said Will Abbey, general manager, physical design group, ARM. "By delivering libraries optimized with features targeting power-efficiency, ARM and UMC are providing SoC designers with a comprehensive set of new tools." "IoT silicon designers are being asked to deliver more highly integrated solutions within more power constrained environments, and more quickly," said Shih-Chin Lin, senior director of IP development and design support division at UMC. "UMC possesses the foundry industry's most robust IoT-specific 55nm technology platform, supported by highly comprehensive ...