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Hard macro IP for Phase-Locked Loop functions in SoC design

Date: 09/05/2015
Silicon IP vendor True Circuits is offering new hard macro IP for Phase-Locked Loop (PLL) functional blocks used in applications such as high-speed SerDes and ADC input clocks. The IP line called "Ultra PLL" features low jitter of <500fs and supports processes of popular semiconductor foundries such as TSMC, GLOBALFOUNDRIES and UMC processes.

The Ultra PLL supports wider frequency range with multiplication factors from 3 to over 250,000, supporting low reference clocks down to 32KHz. It also has precise frequency control with a least 26 fractional bits (at least 10 precise) for high fractional-N resolution. PLL design to generate precise and adjustable frequency spreading with programmable rate and depth to meet tight FCC requirements. True Circuits suggest one PLL can be used for all applications on a SoC.

"The growing complexity of today's SoCs and FPGAs presents chip designers with ever increasing challenges that often result in compromises on features, performance and flexibility", remarked John Maneatis, Ph.D., True Circuits, President. "Our goal is to help chip designers tackle these challenges with a single PLL that offers broad functionality and performance in an easy to use programmable hard macro. Whether the need is ultra low jitter for a SerDes, precise frequency resolution for HDMI or extremely low phase noise for an ADC, our new state-of-the-art Ultra PLL has them covered."

Ultra PLLs are available for chip manufacturing nodes in the range of 65nm to 16nm. The hard macros are available for a per use license fee and no royalty fees with the deliverables include GDSII and LVS Spice netlists, behavioral and synthesis models, Library Exchange Format (LEF) files and extensive user documentation.