Non volatile STT-MRAM circuit for SoCs developed by Toshiba

Toshiba has developed a spin-transfer torque magnetoresistive random-access memory (STT-MRAM) circuit for use in latest processors and system-on-a-chip (SoC) integrated circuits, implementing a 1-Mb class of new magnetic materials. The newly developed memory circuit allows low-power, high-efficiency, high-speed performance in energy-efficient magnetic tunnel junction (MTJ) memory. The proposed memory circuit provides speed performance capable of 3.3-ns access to in-cache memory. The circuit furthermore consumes approximately 80% less power than conventional static RAM (SRAM) as embedded memory. Details of the proposed technology were presented on February 24 at the 2015 International Solid-state Circuits Conference in San Francisco. To solve the power consumption in peripheral memory control circuits and to make memory control circuit components nearly normally-off, Toshiba designed a circuit for sub-100-ns high-speed power shutoff and restoration and confirmed its operation. Toshiba explains "Specifically, to reduce the time for power restoration after shutoff, we divide power shutoff into seven regions, provide power switches for each region, and then allow power shutoff for regions other than those involved in memory operations. In measured values for the main operational mode, the best time for power restoration was confirmed as 22 ns following power shutoff, whic...