Xilinx beats Altera through more than Moore 3D path; FPGA can pack 10 ARM Cortex A9

Xilinx has launched new FPGA device "Virtex UltraScale VU440" having 4 million logic cells which is equivalent to 50 million equivalent ASIC gates, a highest gate count FPGA which has been shipped to its customers. Xilinx claims this new 28 nm chip delivers performance more than its competitors ( so mainly Altera) highest density FPGAs made using nodes smaller than 28 nm. How is it possible? It is more than Moore technology, basically stacking of wafers on a interposer, what is called as 2.5 D technology. Xilinx' stacked silicon interconnect (SSI) technology stacks several (three or four) active FPGA dies side-by-side on a silicon interposer. Production qualified at the 28nm node, the SSI technology is built on TSMC's CoWoS (Chip-on-Wafer-on-Substrate) 3D IC process by integrating multiple components on a single device. Along with 5X more inter-die bandwidth and a unified clocking architecture across slice boundaries, UltraScale 3D IC devices deliver a virtual monolithic design experience for fast implementation and design closure. With this VU440, high-density FPGA applications such as 400G MuxSAR, 400G Transponder and 400G MAC-to Interlaken bridge can be implemented in single chip. The advantageous features in VU440 is, it has ASIC like architecture, where the gate utilisation rate is 90% by supporting advanced routing and ASIC like clocking. Basically interconnec...