Verification tool features seamless flow of SoC design from pre to post-Si

Synopsys announced the Synopsys Verification Continuum platform offering Unified Compile with its VCS and Unified Debug with Verdi across the verification flow, speeding time-to-market by months for complex SoC designs. This tool supports what is called "shift-left" strategies with concurrent practices across pre-silicon verification, post-silicon validation and software bring-up to reduce SoC time-to-market. Verification Continuum offers simulation-like user experience allowing designers to transit between simulation, static and formal verification, emulation, FPGA-based prototyping and debug as required by the verification task. Synopsys says "Existing flows based on individual point tools require extensive setup for each tool in the flow, and weeks or months of effort to move a design between different tools based on varying language support or other requirements. Unified Compile with VCS eliminates this redundant work, saving months of effort in typical project schedules." Also available is Unified Debug based on Synopsys' Verdi3 environment providing consistent debug user experience across the verification flow, optimized with Verification Continuum technologies for even higher productivity. Verdi3 debugs synchronized, mixed-abstraction between SPICE, RTL, transactions and software. Verification Continuum integrates FPGA-based emulation and prototyping seam...