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  Date: 29/09/2014

Verification tool features seamless flow of SoC design from pre to post-Si

Synopsys announced the Synopsys Verification Continuum platform offering Unified Compile with its VCS and Unified Debug with Verdi across the verification flow, speeding time-to-market by months for complex SoC designs.

This tool supports what is called "shift-left" strategies with concurrent practices across pre-silicon verification, post-silicon validation and software bring-up to reduce SoC time-to-market.

Verification Continuum offers simulation-like user experience allowing designers to transit between simulation, static and formal verification, emulation, FPGA-based prototyping and debug as required by the verification task. Synopsys says "Existing flows based on individual point tools require extensive setup for each tool in the flow, and weeks or months of effort to move a design between different tools based on varying language support or other requirements. Unified Compile with VCS eliminates this redundant work, saving months of effort in typical project schedules."

Also available is Unified Debug based on Synopsys' Verdi3 environment providing consistent debug user experience across the verification flow, optimized with Verification Continuum technologies for even higher productivity. Verdi3 debugs synchronized, mixed-abstraction between SPICE, RTL, transactions and software.

Verification Continuum integrates FPGA-based emulation and prototyping seamlessly into mainstream verification flows to save weeks of chip design time. Verification Continuum's Unified Compile technology has been architected to support FPGA-based verification platforms, delivering up to 3X faster compile time for Synopsys' ZeBu Server-3 emulation system.

"AMD's advanced multi-core Accelerated Processor Unit designs require a continuum of verification technologies working seamlessly together to meet growing hardware and software verification requirements," said Alex Starr, fellow & pre-silicon solutions architect at AMD. "Synopsys Verification Continuum represents an important new direction for the industry, and our initial evaluation of the technology indicates it can accelerate design schedules with a more efficient and scalable platform optimized for complex SoC verification and early software bring-up."

"The Verification Continuum requires an optimized software flow combined with the highest-performance, highest-capacity emulation and prototyping hardware," said Victor Peng, executive vice president and general manager of the Programmable Products Group at Xilinx. "Xilinx has raised the bar again with our Virtex UltraScale devices, offering the largest 20nm FPGA in the industry, the XCVU440. We are working closely with Synopsys to optimize our Vivado Design Suite flow to address the unique requirements of hardware-assisted verification users."

"Synopsys' Verification Continuum, developed in close collaboration with market leaders, will enable a new era of SoC verification for the industry," said Manoj Gandhi, senior vice president and general manager of the Verification Group at Synopsys. "The significant verification R&D investments Synopsys has made over the past two years are already showing promising early results towards helping customers reduce time-to-market by months for advanced SoC designs."

Early availability is scheduled for December 2014, with general availability in 2015.

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