28Gbps SerDes evaluation platform for 100G n/w chip design

VLSI design company Open-Silicon launched evaluation board with 28 nm test chip integrating 28Gbps Serializer/Deserializer (SerDes) for quickly designing silicon and systems for 100G networks. The test semiconductor chip features 28Gbps SerDes quad macro, using physical layer (PHY) IP from Semtech, and meets the compliance needs of the CEI-28G-VSR, CEI-25-LR and CEI-28G-SR specifications. “Silicon-proven IP, such as the advanced 28Gbps SerDes PHY developed by Semtech, is central to our success as a leading ASIC solutions supplier,” said Taher Madraswala, president of Open-Silicon. “In selecting IP and IP partners, we take into account not only the overall functionality within the IP and its compatibility with other IP blocks, but also its interoperability within the ASIC tool flow and how reliably it can be manufactured in a high-volume process technology. The Semtech 28Gbps IP satisfies our stringent third-party IP requirements, and provides our ASIC customers with a reliable path to meeting the needs of 100G networks.” “Having silicon results at this important 25G+ threshold is essential for customers to move forward with their plans to develop ASICs for the 100G network build-out,” said Kevin Walsh, director of worldwide marketing, Semtech Snowbush IP Group. “With Open-Silicon, we have a partner that can develop these complicated chips. We have worked closely wit...