Arteris's FlexNoC Composition cuts SoC design time from 18 months to 9

Arteris has announced FlexNoC Composition, a new feature embedded within the FlexNoC interconnect IP, which allows VLSI design engineers to integrate the individual interconnects from all SoC subsystems into one. This technology helps VLSI design teams to work at different locations simultaneously without much of the design flow issue. Arteris says its IP saves development time from 18 months to 9 months for even the most complex SoCs. Arteris explains: FlexNoC Composition allows the SoC architecture to be subdivided for implementation by various specialist design teams, each working independently on their own subsystem. Once all subsystems are complete, each can be integrated into one complete full chip-level FlexNoC interconnect fabric without requiring bridges. FlexNoC Composition works for fully abutted and channeled floor plans. Unlike a hybrid bus or crossbar, FlexNoC Composition re-connects each subsystem seamlessly through a specialized low-latency protocol, Re-assembly is simple, regardless of revisions made to the IP block addressing, transaction protocols, or command sets during the development process. The chip verification process is also easier and faster. These features make the development of a family of derivative chips to meet individual system OEMs’ specific requirements a plug-and-play process. “Arteris continues to advance network-on-chip technolo...