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  Date: 20/10/2013

40 GFLOPs vector floating point DSP for wireless communication

To design a powerful ultra modern wireless base station, you need a high performance computer comparable to a old-style supercomputers to handle multiple types of data received from multiple air interface standards such as LTE, 3G and Wi-Fi. The trend is clearly software defined radio/network, which really requires high performance computing.

The concept once which was popular in supercomputers called vector processing is now making a comeback in communication infrastructure equipment design. The gigaflop performance has become a necessity. There are two popular processing concepts to process multiple data in single instruction. They are Single Instruction Multiple Data (SIMD) and Vector Floating Point (VFP). SIMD is extensively used where in single instruction same operation carried on multiple data in parallel. Whereas in VFP, there is one operation on one set of inputs and returns one output. VFP speeds up the floating point calculation but is said to process sequentially.

By noticing the importance of vector floating point architecture in wireless base stations, DSP IP core vendor Ceva has come out with what it claims as market's first vector floating point DSP. The CEVA-XC4500 features baseband-dedicated instruction set architecture (ISA), IEEE-compliant floating point support on full vector elements delivering up to 40 GFLOPs performance, comprehensive multi-core support, a fully cached architecture and hardware managed coherency. The family called CEVA-XC is designed for base station equipment. Ceva says it has more than 45 baseband design wins to date, including more than 25 design wins for LTE and LTE-Advanced.

CEVA-XC4500 is designed to consume less power, Ceva says it consumes 100mW for LTE 2x2 Pico-Cell baseband processing.

Ceva is collaborating with ARM in making sure-- the chip design with both ARM processor cores and Ceva DSP processor cores get interconnected without bottlenecks or inefficiencies. They want to create a powerful combination of ARM + Ceva computing platform. Some of the ARM's processors support both SIMD and VFP.

There are plenty of new applications which require high performance computing at low-power, examples include heterogeneous cellular networks (HetNet) and cloud RAN (C-RAN). To know more on Ceva's product visit http://www.ceva-dsp.com/CEVA-XC4500.

To give you another news on processor IP release, Imagination has unveiled MIPS P5600 core supporting 128-bit SIMD and hardware virtualization. Imagination claims this processor core takes 30% smaller area on silicon compared to comparable CPU coolers from other competitors.

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