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  Date: 29/09/2013

Not a memory chip, it's a memory cube

The leading memory chipmaker Micron Technology has announced the shipment of 2GB Hybrid Memory Cube (HMC) engineering samples. hybrid memory cube stacks multiple number of DRAM memory dies atop a logic circuit, which are connected through silicon vias. The logic layer helps in fast read/write of the data into stacked multiple DRAM chips so that data is accessed faster at low-power consumption for each bit read/write activity, compared to DDR3 architecture.

Hybrid memory cube can support the high data read/write speeds in case of 100G/400 G systems. The supercomputers can work faster without delay in memory reading and writing. The immediate applications of hybrid memory cube are exascale computing and high-speed networking which require high- bandwidth access to memory, including data packet processing, data packet buffering or storage.

Micron has released 2 GB memory cube built using stack of four 4Gb DRAM die. It can provide a memory bandwidth of 160 GB/s at a 70 percent less energy per bit than existing technologies.

"The Hybrid Memory Cube is a smart fix that breaks with the industry's past approaches and opens up new possibilities," said Jim Handy, a memory analyst at Objective Analysis. "Although DRAM internal bandwidth has been increasing exponentially, along with logic's thirst for data, current options offer limited processor-to-memory bandwidth and consume significant power. HMC is an exciting alternative."

"System designers are looking for new memory system designs to support increased demand for bandwidth, density, and power efficiency," said Brian Shirley, vice president of Micron's DRAM Solutions Group. "HMC represents the new standard in memory performance; it's the breakthrough our customers have been waiting for."

Micron expects 4GB HMC engineering samples to be available in early 2014 with volume production of both the 2GB and 4GB HMC devices beginning later in 2014.
To learn more on the hybrid memory cube technology visit the website of hybrid memory cube consortium at

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