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Cadence GigaOpt reducing SOC physical design time

Date: 15/08/2013
Extremely complex SoC designs at deeper nodes are relying on pre-route software tools to speedup physical design. One such pre-route software tool is GigaOpt from Cadence.

Cadence claims Avago had increased performance of a 28nm networking chip by 57% using GigaOpt technology in the EDI System. Cadence has announced one more semiconductor company Freescale Semiconductor has also taped out 28 nm Power architecture based 12 64-bit e6500 processors integrated SOC chip faster using Cadence' latest release of Encounter Digital Implementation (EDI) System. The T4240 operating at 1.8 gigahertz targets communication networking systems design in applications such as carrier, enterprise cloud computing, military and industrial markets.

“Our T4240 SoC represents a great step forward in our high-performance QorIQ T series product line targeted for demanding networking applications. Cadence’s GigaOpt technology helped us achieve aggressive time to market for our next generation T4240 SoC,” said Ken Hansen, vice president and chief technology officer, Freescale Semiconductor. “We were also able to realize better design performance, smaller silicon area, and improve design team productivity.”

GigaOpt is a new multi-threaded physical optimization technology included as standard in the latest EDI System release for pre-route, post-clock tree synthesis, and post-route optimization. GigaOpt also includes new layer-aware timing-driven net buffering and critical path replacement algorithms which cadence claims it can deliver significant improvements in design performance, area, and power.