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  Date: 04/08/2013

8051 code compatible processor IP both in Von Neumann and Harvard architectures

The most popular 8051 processor IP core can be power-efficiently used in SOC design by using this new IP core from Digital Core Design. Digital Core Design has introduced the soft IP core DP80930 which is binary compatible with 8051 and 80390 instruction sets. The pipelined RISC architecture based IP core can execute 200 million instructions per second by using 8120 logic-gates. The DP80390 is an independent IP core which can be implemented in both ASIC as well as programmable FPGA chips.

The DP 80390 designed to operate with both fast memory inside the chip and slow memory outside the chip. DP 80390 supports up to 8MB of linear code space and 16 MB linear data space. We’ve designed this IP Core with a special concern about performance to power consumption ratio - explains Piotr Kandora, R&D Director at Digital Core Design - and this ratio can be extended by an advanced power management unit (PMU).

Designer can easily choose from two configurations of both Von Neumann, with common program and external data bus and Harvard, where internal data and program buses are separated.

Digital Core Design says the pipelined RISC architecture of the DP80390 executes 85 – 200 million instructions per second, running the Dhrystone 2.1 benchmark from 11.46 to 15.55 times faster than the original 80C51 at the same frequency. - This performance can also be exploited in low power applications – adds Kandora - where the core can be clocked over ten times slower than the original implementation, without performance depletion.

VLSI designers are provided with fully automated test bench and complete set of tests for package validation at each stage of SOC design flow. The core has built-in support for real-time hardware debugger called DoCDT from Digital core design, which provides nonintrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller including register, internal and external program memories and all SFRs including user-defined Peripherals.

The feature-set of this 8051 code compatible processor IP core:

· Software in 100% compatible with 80390 & 8051 industry standards
o LARGE mode – 8051 instruction set
o FLAT mode – 80390 instruction set
· Pipelined RISC architecture enables to run 15.55 times faster, than the original 80C51 at the same frequency
· Up to 14.632 VAX MIPS at 100 MHz
· 24 times faster multiplication
· 12 times faster division
· Up to 256 bytes of internal (on-chip) Data Memory
· Up to 8 MB of linear Program Memory
o 64 kB of internal (on-chip) Program Memory
o 8 MB external (off-chip) Program Memory
· Up to 16 MB of external (off-chip) Data Memory
· User programmable Program Memory Wait States
· User programmable External Data Memory Wait States
· De-multiplexed Address/Data bus, to allow easy memory connection
· Interface for additional Special Function Registers
· Fully synthesizable
· Static synchronous design
· Positive edge clocking and no internal tri-states
· Scan test ready
· 2 GHz virtual clock frequency in a 0.25u technological process.

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