8051 code compatible processor IP both in Von Neumann and Harvard architectures

The most popular 8051 processor IP core can be power-efficiently used in SOC design by using this new IP core from Digital Core Design. Digital Core Design has introduced the soft IP core DP80930 which is binary compatible with 8051 and 80390 instruction sets. The pipelined RISC architecture based IP core can execute 200 million instructions per second by using 8120 logic-gates. The DP80390 is an independent IP core which can be implemented in both ASIC as well as programmable FPGA chips. The DP 80390 designed to operate with both fast memory inside the chip and slow memory outside the chip. DP 80390 supports up to 8MB of linear code space and 16 MB linear data space. We’ve designed this IP Core with a special concern about performance to power consumption ratio - explains Piotr Kandora, R&D Director at Digital Core Design - and this ratio can be extended by an advanced power management unit (PMU). Designer can easily choose from two configurations of both Von Neumann, with common program and external data bus and Harvard, where internal data and program buses are separated. Digital Core Design says the pipelined RISC architecture of the DP80390 executes 85 – 200 million instructions per second, running the Dhrystone 2.1 benchmark from 11.46 to 15.55 times faster than the original 80C51 at the same frequency. - This performance can also be exploited in low power...