Aldec's UVM supporting VLSI verification platform simulates 2-3x faster

Aldec has released latest version of its mixed-language advanced verification platform, Riviera-PRO 2013.06. The enhancements include class hierarchy visualization for UVM-based verification environments helping in increasing verification productivity. “With enhanced UVM support, Riviera-PRO 2013.06 makes it easier for verification teams to deploy class-based Testbench environments”, said Dmitry Melnik, Product Manager, Aldec Software Division. “The new 'Classes' window available with this release provides essential information about the operation of verification environments that are based on the object-oriented library and dynamic data types.” Aldec says Riviera-PRO 2013.06 presents SystemVerilog classes in the form of a hierarchical tree view, integrated with the rest of the IDE for easy cross-probing and navigation, and providing indication of class inheritance, methods, properties, and other important attributes. The new version 2013.06 of Riviera-PRO offers 2—3x average speedup in simulations with code coverage enabled. Featuring SystemVerilog random constraint solver, new UVM-aware debugging tools, and improved simulation capacity, Riviera-PRO 2013.06 increases verification performance, accelerates coverage closure. Riviera-PRO 2013.06 is available now. Aldec has also announced that engineers incorporating high-speed PCI Express data transmission into th...