Aldec's UVM supporting VLSI verification platform simulates 2-3x faster

Aldec has released latest version of its mixed-language advanced verification platform, Riviera-PRO 2013.06. The enhancements include class hierarchy visualization for UVM-based verification environments helping in increasing verification productivity.

“With enhanced UVM support, Riviera-PRO 2013.06 makes it easier for verification teams to deploy class-based Testbench environments”, said Dmitry Melnik, Product Manager, Aldec Software Division. “The new 'Classes' window available with this release provides essential information about the operation of verification environments that are based on the object-oriented library and dynamic data types.”

Aldec says Riviera-PRO 2013.06 presents SystemVerilog classes in the form of a hierarchical tree view, integrated with the rest of the IDE for easy cross-probing and navigation, and providing indication of class inheritance, methods, properties, and other important attributes.

The new version 2013.06 of Riviera-PRO offers 2—3x average speedup in simulations with code coverage enabled.

Featuring SystemVerilog random constraint solver, new UVM-aware debugging tools, and improved simulation capacity, Riviera-PRO 2013.06 increases verification performance, accelerates coverage closure. Riviera-PRO 2013.06 is available now.

Aldec has also announced that engineers incorporating high-speed PCI Express data transmission into their SoC and ASIC designs can accelerate their time-to-market utilizing Northwest Logic PCI Express IP Cores with Aldec’s HES-7 prototyping platform.

“Northwest Logic’s PCI Express IP cores enable designers to quickly create PCI Express-based SoC designs for a variety of markets including embedded applications, server development, communications, and more,” said Aldec HES-7 product engineer, Bill Tomas, “The combination of Northwest Logic’s pre-verified PCI Express IP Cores with the high-speed capabilities of the HES-7 enables design teams to reduce system verification time and the risks of silicon re-spins”.

The HES-7 SoC/ASIC Prototyping Platform is a scalable FPGA-based solution for hardware and software teams developing SoC and ASIC designs up to 96 million ASIC gates. Utilizing the latest in FPGA technology with the Xilinx Virtex-7 family and Zynq SoC, HES-7 provides support for ARM Cortex-based designs with several media interfaces available on-board including: Ethernet, Wi-Fi, Bluetooth, HDMI, and more. HES-7 also has a PCI Express finger available on-board and is able to handle PCI Express Gen2 and Gen31 designs for up to 8 Gb/s serial data rate.

Northwest Logic’s PCI Express Solution provides a robust and proven platform for developing PCI Express 3.0/2.1/1.1 based products. This high-performance, easy-to-use solution includes a controller core (Expresso 3.0 Core), DMA core (Expresso DMA Core), and drivers (Expresso DMA Drivers).

“HES-7 provides a lot of capability in a little package,” said Northwest Logic’s president, Brian Daellenbach, “The dual Virtex-7 2000T and ARM support, in combination with the Northwest Logic PCIe Cores, enable large SoC, PCIe-based designs to be quickly prototyped with a minimum of design partitioning”.