Chip-design EEs can monitor V/I and EM issues while layout is created

Cadence Design Systems is offering in-design electrical verification capability in its Virtuoso Layout Suite for Electrically Aware Design (EAD). VLSI design teams can monitor electrical issues while a layout is created, rather than wait until the layout is completed before verifying that it meets the original design intent. Cadence claims Virtuoso Layout Suite EAD allows engineers to reduce their circuit design cycle by up to 30 percent while optimizing chip size and performance. Custom IC design engineers can electrically analyze, simulate and verify interconnect decisions in real time, resulting in layout that is electrically correct-by-construction. This real-time visibility lets engineers reduce conservative design practices – or “over-design” – that can negatively impact a chip’s performance and area, suggests Cadence. The key features Virtuoso Layout Suite EAD according to Cadence includes: The ability to capture currents and voltages from simulations run in the Virtuoso Analog Design Environment, and pass that electrical information forward into the layout environment Management capabilities that enable circuit designers to set electrical constraints (like matched capacitance and resistance) and allow layout designers to observe in real-time if these constraints are being met A built-in interconnect parasitic extraction engine that rapidly evaluates layout...