Memory and logic libraries for optimal design of SoC

The new DesignWare HPC (High Performance Core) Design Kit from Synopsys packs high-speed and high-density memory instances and standard cell libraries for SoC chip design engineers to optimize their on-chip traditional processing, graphic processing and digital signal processing IP cores for maximum speed, smallest area or lowest power or to go for a optimum balance of speed power and size of SoC chips. The DesignWare contains all the physical IP elements for VLSI design engineers to implement a complete SoC including standard cells, SRAM compilers, register files, ROMs, datapath libraries and Power Optimization Kits (POKs). Options for overdrive/low- voltage process, voltage and temperature (PVT) corners, multi-channel cells, and memory built-in self-test (BIST) and repair are also available. The DesignWare HPC Design Kit adds performance-, power- and area-optimized standard cells and memory instances tuned for the special speed and density requirements of advanced CPU, GPU and DSP cores. "The physical IP used for implementing processor cores has a tremendous impact on the achievable power, performance and area of the design," said Nianfeng Li, corporate vice president of design methodologies and program management at VeriSilicon. "When we consider all the factors that contribute to an optimized implementation, the DesignWare Duet Embedded Memories and Logic Libraries h...