Memory and logic libraries for optimal design of SoC
The new DesignWare HPC (High Performance Core) Design Kit from Synopsys packs high-speed and high-density memory instances and standard cell libraries for SoC chip design engineers to optimize their on-chip traditional processing, graphic processing and digital signal processing IP cores for maximum speed, smallest area or lowest power or to go for a optimum balance of speed power and size of SoC chips.
The DesignWare contains all the physical IP elements for VLSI design engineers to implement a complete SoC including standard cells, SRAM compilers, register files, ROMs, datapath libraries and Power Optimization Kits (POKs). Options for overdrive/low- voltage process, voltage and temperature (PVT) corners, multi-channel cells, and memory built-in self-test (BIST) and repair are also available. The DesignWare HPC Design Kit adds performance-, power- and area-optimized standard cells and memory instances tuned for the special speed and density requirements of advanced CPU, GPU and DSP cores.
"The physical IP used for implementing processor cores has a tremendous impact on the achievable power, performance and area of the design," said Nianfeng Li, corporate vice president of design methodologies and program management at VeriSilicon. "When we consider all the factors that contribute to an optimized implementation, the DesignWare Duet Embedded Memories and Logic Libraries have been a primary contributor to the performance gains we realized on the recent hardening of a leading CPU core. The new DesignWare HPC Design Kit contains the specialty cells and SRAMs we need to achieve the highest possible performance on advanced processor cores while minimizing area and power consumption."
"DSPs are a fundamental component of every advanced electronic product, from smartphones and tablets to smart TVs and base stations, and each design has unique optimization requirements," said Eran Briman, vice president of marketing at CEVA, Inc. "In addition to extreme performance, designers rely on our DSP cores to consume as little power and occupy as little silicon area as possible. We look forward to continued collaboration with Synopsys in helping our mutual customers achieve their strict design goals."
Synopsys says the HPC Design Kit contains fast cache memory instances and performance-tuned flip-flops that enable speed improvement of up to 10 percent over the standard Duet package. To minimize dynamic and leakage power as well as die area, the new kit provides area-optimized and multi-bit flip-flops and an ultra-high-density two-port SRAM, delivering demonstrated reductions in area and power of up to 25 percent while maintaining processor performance, claims Synopsys.
Optimized design flow scripts and expert core optimization consulting, including FastOpt implementation services, are also provided by Synopsys to save time.
"Designers using any of Imagination's IP, including PowerVR graphics and video, MIPS processors and Ensigma communications processors, will ultimately be able to reap benefits from leveraging Synopsys' HPC Design Kit, thanks to their deep experience working with Imagination and delivering services to our customers over many years," added Mark Dunn of Imagination. "Through projects including our strategic collaboration with Synopsys, we're putting practical solutions in place to help our customers achieve performance-, power- and area-optimized designs utilizing our IP in the shortest time."
"Designers implementing processor cores must make tradeoffs in speed, power and area that will result in the best implementation for their specific application, and physical IP plays an important role in achieving that optimum design," said John Koeter, vice president of marketing for IP and systems at Synopsys. "We have worked closely with leading customers and IP partners that implement a broad range of processor cores to gain insight on how to achieve the absolute best results on their design and reflected that collective learning in the new DesignWare HPC Design Kit. In one package, designers now have access to the specialty cells and memories they need to optimize their CPU, GPU and DSP cores across the full speed, power and area spectrum."
The DesignWare HPC Design Kit to be available for leading 28-nm processes starting in July 2013.
Learn more about the DesignWare HPC Design Kit: http://www.synopsys.com/hpc-ip.