Accelera delivers revised version of standards for low power IC design

Low power VLSI design developed in one EDA software/platform, if not easily portable to other EDA software/platform causes bottlenecks in chip design, making the team to manually convert the code. This made chip design industry to look for a standard in writing code for low power SoC design. Accellera has done an appreciable job in delivering the standard for such needs. Accellera Systems Initiative (Accellera) in partnership with IEEE Standards Association (IEEE-SA) has delivered the revised version of IEEE 1801-2013 "Standard for Design and Verification of Low Power Integrated Circuits Language Reference Manual", which is now available through the IEEE Get Program, which grants public access to view and download select IEEE standards at no charge. The standard known as UPF (Unified Power Format) makes low power design specifications portable from one platform to other. The format said to provide the ability to specify the supply network, switches, isolation, retention and other aspects relevant to power management of an electronic system. The four standards available from Accellera in partnership with the IEEE-SA are: o IEEE 1801-2013-Standard: Standard for Design and Verification of Low Power Integrated Circuits o IEEE 1800-2012 Standard: SystemVerilog Unified Hardware Design, Specification, and Verification Language o IEEE 1685 Standard: IP-XACT, St...