Tool provide detailed info about the post-layout interconnections on SoC chips

Concept Engineering has added a new SPEF (standard parasitic exchange format) interface to their VLSI debugging tools, SpiceVision PRO and StarVision PRO. VLSI engineers can debugg their chip design by converting their SPICE netlists and SPICE models into a trasistor level circuit diagrams/schematics using Concept Engineering 's SpiceVision PRO EDA software tool. Another tool StarVision PRO for Concept is an integrated debugging cockpit for Mixed-Signal design, makes analysis and debugging of complex SoC (system on chip) and IC (integrated circuit) designs easy and more transparent. Concept says the newly added SPEF interface, and the already-available DSPF (Detailed Standard Parasitic Format) interface, give design engineers using SpiceVision PRO and StarVision PRO an easy way to analyze and explore parasitic structures in order to better understand, manage and optimize timing, signal integrity or IR-drop within their designs. The SPEF file format is an IEEE standard to define parasitic networks and contains precise information about interconnections and the related parasitic components. Concept Engineering says its new SPEF interface provides engineers with very detailed information about the post-layout interconnections on their chips, allowing them to easily visualize and explore parasitic netlists and to precisely locate and understand post-layout problems. In ad...