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  Date: 23/05/2013

Serial RapidIO 2.2 Endpoint Core from Praesum for ARM AMBA 4 AXI4

Praesum Communications has announces general availability of its Serial RapidIO 2.2 Endpoint Core for ARM AMBA 4 AXI4. "The Praesum Communications AXI to RapidIO interface is a key enabling technology required by ARM-based processing solutions to operate in these applications," said Sam Fuller, Executive Director of the RapidIO Trade Association. "Praesum is an active contributor to the RapidIO specification development, and a long time provider of RapidIO technology to the industry."

Praesum says "The ARM architecture is moving beyond its historical mobile phone roots and into ASIC, ASSP and FPGA devices from multiple vendors targeting mil-aero, communications infrastructure and data center applications," continues Fuller. "These applications often rely on RapidIO as a key high-performance low-latency interconnect."

The Serial RapidIO Endpoint Core for AMBA 4 AXI4 provides the following benefits:

Direct, memory mapped, connection of RapidIO IO Logical layer functions to AXI4 interconnect.
Complete implementation of Rev. 2.2 of the RapidIO Physical Layer LP-Serial protocol.
Implements RapidIO Error Management Extensions.
Supports 1x, 2x, and 4x link widths.
Management Entity with integrated decoder for RapidIO maintenance transactions.
Management Entity supports optional soft packet interface that enables software implementations of logical layer functions.
Praesum's Serial RapidIO 2x Endpoint IP Core is available in two forms: As Verilog RTL source code or as compiled netlists for Xilinx 7 series FPGAs.

Specific technical benefits of the release on the Xilinx platform include:

Complete support for Vivado and IP Integrator design flows.
True push-button timing closure at all supported data rates.
Demo design available for the Xilinx Zynq-7000 SoC ZC706 Evaluation Kit.
Support for other FPGA platforms will be announced early this summer.

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