FPGA fabric and ASIC core twined in a chip/module, a recipe for smart systems

When an engineer designs a system in today's world of changing specifications, changing standards and changing interfaces, the design can only be made last longer by keeping as much flexibility as possible. And in a design everything not going to change. So there is something designer can do manage with ASIC/ASSP and for some, FPGA is necessary. All these years engineers have used to the combination of ASIC and ASSP along with FPGA. The change now engineers are really liking is FPGA vendors are offering both FPGA fabric and ASIC like hardwired logic in single IC (ARM Cortex based hard processors), which is called as Programmable SoC. Krishna Rangasayee, senior vice president and general manager of the Xilinx Communication Business Unit says ASICs and ASSPs in applications like OTN have been disappearing at a surprisingly rapid pace due to the escalating cost of design, wide variance in device requirements, and the need for much greater levels of intelligence and adaptability. This is big design trend where engineers are adopting to improve their design efficiency. Their complete and complex logic design is more inside the programmable SoC and less on the printed circuit board. With 3D stacking of pure-FPGAs with programmable SoCs, there is hardly anything digital outside the chip. The PC board design is going to be more of wiring analog/ mixed signal, power supply ICs, se...