Electronics Engineering Herald                  ADVT
Home | News | New Products | India Specific | Design Guide | Sourcing database | Student Section | About us | Contact us | What's New
Processor / MCU / DSP
Logic and Interface
Power-supply and Industrial ICs
Automotive ICs
Cellphone ICs
Consumer ICs
Computer ICs
Communication ICs (Data & Analog)
RF / Microwave
Subsystems / Boards
Reference Design
Software / Development kits
Test and Measurement

New Products

  Date: 25/02/2013

Panasonic maximize the transistor performance for 60GHz operation

Panasonic has developed technologies to reduce performance errors and maximize the transistor performance in chips for multi-gigabit wireless utilizing the 60GHz wireless band, which is expected to be the future of high-speed wireless communication. The transceiver LSI also features an integrated miniaturized module including an antenna, which contributes to the realization of stable high speed wireless communication for mobile devices.

The chipset incorporates built-in self-calibration to compensate for performance errors, improving the modulation accuracy more than 1.5 times. This makes it possible to reduce the circuit design margin, leading to the improvement of the stability of wireless communications with less than 1W power consumption. By integrating the transceiver LSI into the miniaturized module, the chipset can be implemented in mobile devices, enabling the easy exchange of the rich content, such as high definition videos, among mobile devices wirelessly.

The developed technology has the following features.
Incorporates built-in self-calibration to compensate for performance errors in millimeter wave wireless circuits.
Employs signal processing circuits which equalize the distorted received signal with more than 50% power reduction compared to the conventional approach.
Integrates the transceiver LSI in the miniaturized module including the transmit antenna and the receive antenna (size: 10mm x 10mm).

This development is based on the following new technologies.
Built-in self-calibration for the transmitter and the receiver which reuses existing circuit blocks to minimize the chip area.
Unique low power frequency domain equalizer which significantly reduces circuit size by using a newly proposed signal processing algorithm.

Panasonic holds 48 Japanese patents and 46 overseas patents, including pending applications, for this development.

This result was supported in part by the "research and development project for expansion of radio spectrum resources" of The Ministry of Internal Affairs and Communications, Japan. A part of this release has been presented at IEEE International Solid-State Circuits Conference 2013 at San Francisco on February 20th. Fast File Transfer Demo has also been given at Industrial Demo Session at the conference on the same day.
More on the Technology
1. Built-In Self-calibration which reuses multiple circuit blocks required for compensating performance variations

The chipset employs the transmitter calibration which automatically detects the frequency dependent amplitude errors in the transmitter path and compensates for the errors by the baseband signal processing. It also integrates the auto calibration to compensate the quadrature error3 for minimizing the modulation/demodulation performance as well as the auto calibration to compensate for the error in the transmit power control. With those technologies, the chipset has successfully minimized performance degradations due to process and supply voltage variations, which have been a serious problem for mass production especially at millimeter wave frequencies. The proposed calibration reuses existing circuit blocks to minimize the chip area. This technology improves yields for mass production and contributes to lower the chip cost.
2. Low power frequency domain equalizer which employs the newly proposed signal processing algorithm to reduce circuit size significantly

By estimating the channel characteristics, this block equalizes the frequency distortion due to the multipath4 delay spread. This signal processing normally requires huge computation, which makes it difficult to implement in the mobile devices. Panasonic has developed the unique signal processing algorithm to shrink the size of FFT and IFFT5, resulting in the significant reduction in the computational complexity. Combined with the optimized algorithms for selecting operating blocks, the proposed approach achieved more than 50% power savings compared to the conventional one.

1. WiGig (Wireless Gigabit Alliance)
Established in May 2009, this industry group (consisting of various PC, Home appliances, mobile devices as well as semiconductor companies) has been working actively in the 60 GHz area to create a standard for high speed wireless communication targeting above 1 Gbps, providing interoperability verification, as well as making contribution to the IEEE802.11ad standardization. Its home page is: (http://wirelessgigabitalliance.org/)

2. IEEE802.11ad
The IEEE802.11 is a Working Group that defines a set of standards for Wireless Local Area Network. The Task Group IEEE802.11ad has developed a standard specification for next generation high speed communication of above 1Gbps in the 60GHz frequency band.

3. Quadrature Error
The amplitude and phase error between 0 and 90 degree signals used for digital modulation and demodulation.

4. Multipath
The propagation phenomenon that results in radio signals reaching to the receiver by two or more paths due to the reflection by objects such as a wall and a floor.

Abbreviation of the Fast Fourier Transform, which is the widely used algorithm to convert the digital signals from a time domain to a frequency domain. The reverse conversion is called IFFT (Inverse FFT). The computational complexity increases rapidly as the data size becomes larger.

Source: Panasonic

Home | News | New Products | India Specific | Design Guide | Sourcing database | Student Section | About us | Contact us | What's New
©2010 Electronics Engineering Herald