New memory arch R+ LPDDR3 from Rambus supports 3200 Mbps speed

Rambus has announced its R+ LPDDR3 memory architecture for use in designing mobile electronics. R+ LPDDR3 architecture features both a controller and a DRAM interface to reduce active memory system power by up to 25% and supports data rates of up to 3200 megabits per second (Mbps), which is double the performance of existing LPDDR3 technologies.

“Each generation of mobile devices demands even higher performance with lower power. The R+ LPDDR3 technology enables the mobile market to use our controller and DRAM solutions to provide unprecedented levels of performance, with a significant power savings,” said Kevin Donnelly, senior vice president and general manager of the Memory and Interface Division at Rambus. “Since this technology is a part of our R+ platform, beyond the improvements in power and performance, we’re also maintaining compatibility with today’s standards to ensure our customers have all the benefits of the Rambus’ superior technology with reduced adoption risk.”

Rambus explains the seed to the improved power and performance offered by the R+ LPDDR3 architecture is a low-swing implementation of the Rambus Near Ground Signaling technology. Essentially, this single-ended, ground-terminated signaling technology allows devices to achieve higher data rates with significantly reduced IO power, describes Rambus. The R+ LPDDR3 architecture is backward compatible with LPDDR3 supporting same protocol, power states and existing package definitions and system environments.

Additional key features of the R+ LPDDR3 include:
1600 to 3200Mbps data rates
Multi-modal support for LPDDR2, LPDDR3 and R+ LPDDR3
DFI 3.1 and JEDEC LPDDR3 standards compliant
Supports package-on-package and discrete packaging types
Includes LabStation software environment for bring-up, characterization, and validation in end-user application
Silicon proven design in GLOBALFOUNDRIES 28nm-SLP process