Enhanced AES crypto engine from Barco Silex

Barco Silex, Barco's center of competence for electronic design, has released enhanced version of its multi-purpose AES crypto engine.

Barco Silex says the BA411E supports a wide range of ciphering modes and offers an outstanding ratio performances/resources for ASIC and FPGA.

The key features of this security VLSI IP core includes:

The Advanced Encryption Standard (AES) algorithm is used to encrypt and decrypt data for transfers through unsecured channels. Example of this core is securing an USB 3.0 storage device data encryption up to 5Gbps.

CCM mode in this engine combines the well-known CTR mode for encryption and the CBC mode to generate or verify a Message Integrity Code (MIC). Both modes can be easily computed in parallel also using a single core can lead to more compact solutions.

"When there is no dependency between the encryption of two consecutive blocks, a pipelined architecture that processes several blocks simultaneously will deliver the highest performances. Unfortunately, the increased latency of pipelined architectures is a real drawback in feedback mode. The only way to achieve higher throughput is to reduce the critical paths," says Philippe Lorent, Product Manager at Barco Silex.

He continues: "Our BA411E IP has been designed to support multi-pipelined architectures and multiple data path configurations. In CCM mode, a single dual-pipelined core that supports interleaved capabilities will make the same job as two cores working in parallel without any performance penalty. Such configuration can process up to 1.5Gbps with less than 18kgates @ 400MHz in a standard 90nm ASIC technology. In CTR mode, the same dual-pipelined core will reach 3Gbps. This optimized architecture is a well-suited configuration for high-speed GCM applications."

"In addition to this high level of flexibility, the BA411E offers the possibility to efficiently implement S-boxes as simple logic for ASIC or as memories for FPGA. This means that the same level of flexibility and performance can be easily obtained on any existing FPGA technology as well as on any ASIC process" Philippe Lorent continues.

"Offering scalable, portable and flexible solutions with optional interleaved capabilities is the best guarantee to meet customer's requirements in all cases." Thierry Pauwels, Marketing & Sales support for IP Business at Barco Silex, adds,. "The design team really focused on developing an easy-to-use solution. The BA411E provides suitable interfaces like AXI4-Stream. It also offers useful features that make the integration of the crypto engine easier. The core can be automatically stalled when the input data are not available or when the output FIFO is full. Additionally, a "null cipher" mode can be applied on blocks that are not part of the payload."