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Date: 16th Jun 2011

Memory chips transit from a zero-power state to a 5+ Gb/s data transfer rate in 5 ns

Rambus Inc. has developed fast power-on, low-power clocking technology for memory chips. Rambus says this technology is capable of transitioning from a zero-power idle state to a 5+ Gb/s data transfer rate in 5 nanoseconds (ns) while achieving active power of only 2.4mW/Gb/s.

Rambus Labs has used feed-forward architecture to achieve extremely fast turn-on and turn-off, simplifying the system design and significantly reducing the overall system power requirements.

"Through this work, we've dramatically reduced system complexity and have saved substantial power while increasing performance to more than 5Gb/s per differential link," said Jared Zerbe, technical director at Rambus. "When incorporated into an SoC-to-memory interface, or SoC-to-SoC link, this development can significantly reduce the memory system power and time-to-first access, driving us closer to the vision of energy proportional computing."

Mr. Zerbe unveiled the results of this development today at the VLSI Circuit Symposium 2011 in Kyoto Japan. For more information visit http://www.vlsisymposium.org/


 
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