SLEC from Calypto does C to C, C to RTL and RTL to RTL equivalency checks

Calypto Design Systems, Inc., has announced version 6.0 of SLEC, its Sequential Logic Equivalence Checking platform. The SLEC platform formally verifies Register Transfer Level (RTL) designs and system-level models without using testbenches or assertions. SLEC performs C to C, C to RTL and RTL to RTL equivalency checks, relieving the VLSI chip designer from manually rewriting testbenches and re-running exhaustive regression simulations.

"SLEC has established itself as the only formal sequential equivalence checker for high level synthesis (HLS) flows, as well as for RTL-level sequential changes done by designers to close timing or power budgets," remarked Anmol Mathur, CTO, Calypto. "The enhancements in SLEC 6.0 significantly improve SLEC's capacity and expand its usage across all the different SLEC flows."

What's New in SLEC version 6.0:
SLEC System HLS, which compares C models to automatically generated RTL models, improves interoperability by adding support for SystemC 2.2 and for all the supported vendors and their tools -Mentor Catapult, Cadence CtoS, Forte Cynthesizer. In addition, SLEC now has full integration and support for Catapult SystemC. The integration with CtoS has been enhanced with automatic inferencing of latency and throughput refinements, users no longer have to manually input this timing information. For Forte users, flow enhancements have been made involving external memory interfacing in pipelined designs.