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Date: 6th Feb 2011

New HDL debugging technology called Mirror-Box from Aldec

As the complexities of the semiconductor chips growing, there is also growth in bugs. To help VLSI chip designers to reduce their verification cycles, VLSI design EDA software vendor Aldec Inc. adds the Mirror-Box debugging technology to streamline debugging during hardware-assisted simulation. The Mirror-Box technology allows any component, at any hierarchical level, to be mirrored such that two implementations of the same component can be simulated: one implementation is the original RTL code which resides in the HDL Simulator and the other is its FPGA counterpart which resides in the hardware board. This suppose to save significant resources for VLSI verification engineers

"As a technology-leader in the electronic design verification industry, Aldec is committed to meeting the growing needs of verification engineers by adding new debugging technologies like Mirror-Box. The ability for engineers to quickly validate and compare differences between simulation model and actual hardware without rerunning Synthesis and P&R increases their overall productivity in debugging." said Dave Rinehart, Vice President of Aldec, Inc.

Mirror-Box Benefits as listed by Aldec includes:

1. Time Savings - Verification engineer can switch between RTL code and FPGA hardware models     without having to rerun Synthesis and Place and Route. This eliminates the need to rebuild the FPGA     several times during debugging, which ultimately helps in detecting more errors and bugs per day.
2. In-Hardware Validation - Runtime comparison of component outputs between RTL code and actual     hardware, allowing detection of discrepancies between the simulation model and real hardware
3. Flexibility - Verification engineer can make changes to the design component selected as Mirror-Box      in HDL simulator while the rest of the design runs in the FPGA hardware.
For more information, including white papers and webinars, visit www.aldec.com/products/HES.


 
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