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Date: 21st Nov 09

 Actel's high configurable DSP IP cores expand its RTAX-DSP FPGAs

Actel has announced the expansion of its RTAX2000D and RTAX4000D DSP FPGAs with new configurable DSP IP cores. The new cores create common DSP functions such as filters (FIR, IIR) and transforms (FFT, IFT, DCT). Using a graphical user interface (GUI) embedded in Actel's Libero Integrated Design Environment (IDE), and targeting RTAX-DSP space-flight FPGAs.

"By providing a simple but powerful user interface, these configurable DSP cores greatly simplify and shorten the design cycle for DSP applications targeting our new RTAX-DSP FPGAs for space-flight applications," said Ken O'Neill director, high reliability product marketing at Actel. "These new offerings expand the horizons of the RTAX series of FPGAs, which already have a well-established space-flight track record."

The three new DSP IP cores multiplier, multiplier with adder or subtractor, multiplier with accumulator, which are supported through software dialog windows allowing for the quick selection and configuration of multiple common DSP functions.

The configurable DSP IP cores generate structural netlists in either Verilog or VHDL and can be easily instantiated into a complex RTAX-DSP FPGA design using Actel's Libero IDE and SmartDesign graphical block system design creation tool. Comprehensive handbooks are available to assist designers in building various DSP functions.

The IP cores take advantage of the embedded mathblocks available in RTAX-DSP devices. Each mathblock contains a 18x18 bit hardware multiplier, plus a 41-bit internal adder-subtractor and register that can be configured for accumulating multiplier results. The multiplier can be broken into two 9x9 multipliers when less precision and more multipliers are needed. A number of different pipelining options are available, with optional registers on all inputs and outputs. Mathblocks have cascade outputs and inputs for common applications like FIR filters, they may be chained for maximum performance, leaving FPGA fabric resources free. RTAX-DSP devices have up to 120 mathblocks, each of which can perform full-precision multiplications at up to 125 MHz and has built-in protection against radiation-induced single event upsets (SEU) and single event transients (SET).

Price: At $2495 per seat
Availability: The cores are available immediately and are included with an Actel Libero IDE Platinum software license

Node-locked and floating licenses are available.

For more details visit www.actel.com

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