Design of Pipeline Analog to Digital Converter
Vivek Tripathi - Senior Staff Engineer , STMicroelectronics
Chandrajit Debnath - Principal Engineer,, STMicroelectronics
Rakesh Malik - Senior Group Manager, STMicroelectronics
The pipeline analog-to-digital converter (ADC) architecture is the most popular topology for video processing ,telecommunications ,digital imaging etc. designs because its speed is comparable to the parallel or flash architecture, whereas the implementation area and power dissipation are significantly smaller.
Both advantages stem from the concurrent operation of the stages, that is, at any time, the first stage operates on the most recent sample while all other stages operate on residues from previous samples. Once the pipeline is primed, converted digital data are always available at every clock cycle.
Also, since the stages operate concurrently, the number of stages used to obtain a given resolution is not constrained by the required throughput rate. Therefore, under some constraints (such as the total resolution), the number of stages may be chosen to minimize the required die area.
Like other ADC architectures, the pipeline ADC power consumption increases with required signal bandwidth, thus making it one of the major contributors to power consumption in a wideband digital video receiver subsystem. Pipeline ADC’s are used in high Speed(10 MSPS -500 MSPS) data acquisition systems e.g. Low power mobile, cable front end, medical equipment, WiFi, Set Top Box, WLAN etc. SAR ADCs are used for Low speed (1MSPS- 10MSPS) data acquisition systems e.g. Automotive, Battery management , Microcontrollers etc. Sigma-Delta ADCs are used in audio applications. For sensor applications,Industrial control & DC measurements either SAR or Sigma delta ADCs are used depending upon the accuracy & speed. For RF applications(GHz data acquisition ) , Flash ADC is used. This paper will focus on the design technique & concerns of Pipeline ADC.
Fig. 1 shows a block diagram of a general pipelined ADC with k stages. Each stage contains a sample-and-hold amplifier (SHA), a low-resolution analog-to-digital sub-converter (ADSC), a low-resolution digital-to-analog converter (DAC), and a subtractor. To begin a conversion, the input is sampled and held. The held input is then converted into a digital code by the first-stage low-resolution flash A/D converter and back into an analog signal by the first-stage low-resolution D/A converter. The difference between the D/A converter output and the held input is the residue that is amplified and sent to the next stage where this process is repeated. At any instant, while the first stage processes the current input sample, the second stage processes the amplified residue of the previous input sample from the first stage. Because sequential stages simultaneously work on residues from successively sampled inputs, the digital outputs from each stage correspond to input samples at different times. Digital latches are needed to synchronize the outputs from different stages.
Fig.1 :Block diagram of Pipeline ADC
2. BIT/STAGE PIPELINE ARCHITECTURE:
Fig 2 :Ideal Transfer Function of a 2-bit Pipelined Stage
The stage gain is 4x to maximize the dynamic range of the subsequent stage, and to allow for reuse of the reference voltages.
An error in the stage ADC threshold (due to an offset) alters the transfer function as shown in Fig 3
Thus threshold errors lead to stage outputs that exceed the full-scale input to the subsequent stage. This will saturate the second stage and cause missing information. To eliminate thisproblem, one can increase the range of the second stage sub-ADC or equivalently reduce the inter-stage gain of the first stage to tolerate sub-ADC error.
When the interstage gain is reduced to 2, the transfer function becomes as shown in Figure 4.
Fig.4 :Transfer Function with Interstage Gain of 2 and sub-ADC Error
This allows the sub-ADC error to be as large as /4 and the output is still in the input range of thefollowing stage. However, when a sub-ADC error is present without digital correction, the error will appear in the final digital output. Now, assume the first stage is ideal, with a full scale input to the first stage, the output is only between – /2 & /2 , leaving an extra bit on top and bottom of the per-stage resolution. Digital correction simply utilizes the extra bit to correct the overrangingsection from the previous stage.
For example, when one of the sub-ADC thresholds has an offset, the output of the first stage will exceeds /2 . The second stage, sensing the overranging, will increase the output by one LSB. This bit will cause the first stage output to increase by one LSB during the digital correctioncycle. In the same way, when the output of the first stage drops below – /2 , the second stage will sense the overranging and subtract one LSB during digital correction cycle. With this method, the sub-ADC error, as large as /4 , in the stage can be corrected by the following stage with digital correction( adding or subtracting a bit from the digital output depending on whether the error was an over or under range error).
Subtraction can be eliminated by adding 1/2-leastsignificant-bit (LSB) offsets in both the ADC andDAC .The ADSC offset uniformly shifts the location of the decision levels to the right by 1/2 LSB, and the DAC offset shifts the x axis of the plot up by 1/2 LSB. If the DAC and SHA are ideal and the interstage gain is 2, the amplified residue (Fig. 5) remains within the conversion range of the next stage when the ADSC nonlinearity is between ±1/2 LSB. Under these conditions, errors caused by the ADSC nonlinearity can be corrected, and the correction requires either no change or addition. This is true because the offset introduced into the ADSC shifts the decision levels to the right by 1/2 LSB, and if nonlinearity can shift them back to the left by no more than this amount, the digital output is always less than or equal to its ideal value.
Fig5: Vref/4 offset to eliminate digital subtraction
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